International Business Machines Corporation

Sidney James Manning

Maximino Aguilar, Jr

James Michael Stafford

David John Erb

Michael Norman Day

Michael A Paolini

Mark Richard Nutter

James Anthony Pafumi

Robert Paul Stelzer

Michael Stan Gowen

Timothy Howard White

A method that optimizes system performance using performance monitors is presented. The method gathers thread performance data using performance monitors for threads running on either a first ISA processor or a second ISA processor. Multiple first processors and multiple second processors may be included in a single computer system. The first processors and second processors can each access data stored in a common shared memory. The gathered thread performance data is analyzed to determine whether the corresponding thread needs additional CPU time in order to optimize system performance. If additional CPU time is needed, the amount of CPU time that the thread receives is altered (increased) so that the thread receives the additional time when it is scheduled by the scheduler. In one embodiment, the increased CPU time is accomplished by altering a priority value that corresponds to the thread.

Adjusting CPU time allocated to next thread based on gathered data in heterogeneous processor system having plurality of different instruction set architectures

A method for visually displaying an indicator for preceding and succeeding source code lines being executed within a graphical debugging environment. The method includes displaying within a GUI source code lines for a segment of currently examined source code, displaying a visual indicator that is associated with a presently examined source code line, and determining a previously examined source code line, wherein the location of the previously examined line of source code is determined by the use of information that is associated with the previously examined line of source code. The method further includes displaying a visual indicator that is associated with the previously examined line of source code, determining a next source code line that is to be examined, and displaying a visual indicator that is associated with the next source code line that is to be examined.

Method for visually indicating preceding and succeeding source code lines that are executed in a graphical debugging environment

The present invention provides for an apparatus employed to debug a program operating in a supplemental processor when the processor's registers are not readable directly by the debugging operation of a main processor. A program operating in main memory halts due to operational errors. The program code lines save to a cache. In the main processor, a pool of memory is reserved. A copy of the data from the nominally inaccessible supplementary processor registers also transfers to the reserved storage area for processing of the program needing debugging. After the program debugging is complete, a copy of the contents of the memory pool is restored to the memory of the target supplemental processor. A copy of the local store register state and remaining local store data returns to main memory.

Method and apparatus for debugging a program on a limited resource processor

Program debug method and apparatus

A method and apparatus is provided for analyzing performance of a computer or data processing system, during the time that a specified task is running on the system. The analysis is used to furnish a system user with a list of proposed hardware component upgrades that would improve system performance in various respects, each being accompanied by a parameter value indicating the improvement a particular upgrade would provide. Usefully, listed upgrades are made available over the Internet, for purchase by system users. In an embodiment directed to a method, for use with a computer system comprising a configuration of hardware components, selected hardware components are monitored as the system performs a specified task. This is done to acquire statistics representing the operation of respective selected components. The statistics are processed, to identify at least one selected component that impedes the system in performing the task. An upgrade of the identified component is then proposed, together with an indication of the improvement that would result if the upgrade is made.

Method and apparatus for analyzing computer system performance and proposing hardware component upgrades

A system and method for using a processor thread as a debugger is presented. A computer system boots up and initiates a debugger thread. The debugger thread loads a robust, debugger operating system and executes the debugger operating system. Once the debugger thread is functioning, the debugger thread invokes an operational thread. In turn, the operational thread loads a primary operating system and may run various applications. While the operational thread executes the primary operating system and the applications, the debugger thread monitors the operational thread for proper functionality. When the operational thread crashes or terminates, the debugger thread retrieves operational data from the operational thread and provides the operational data to a software developer for analysis.

System and method for processor thread for software debugging

A method and system for controlling access to an adapter, such as a graphics adapter, are disclosed. The method includes querying an adapter lock with a first thread. Thereafter, responsive to determining that the lock indicates the first thread does not have access to the adapter, a sequence to obtain access to the adapter is initiated where the sequence includes writing the adapter context corresponding to the first thread. The, sequence may include a ring 3 to ring 0 transition. The method also includes, in response to determining that the lock indicates the first thread has access to the adapter, communicating to the adapter with the first thread without invoking the sequence to obtain access to the adapter. In one embodiment, querying the adapter lock includes writing a first word of the adapter lock using an atomic operation. The method may further include writing a set of command buffers with the first thread and, responsive to determining that the first has access to the adapter, transferring the commands buffers to the adapter. In one embodiment, the sequence to obtain access to the adapter includes the first thread obtaining ownership of a mutex lock prior to updating the adapter context. The sequence to obtain access to the adapter may include updating the adapter lock status to indicate the first thread having access to the adapter.

Growing community of inventors

Austin, TX, United States of America

Sidney James Manning