Micron Technology Incorporated

Sidhartha Gupta

Naveen Kaushik

Pankaj Sharma

Kyle A Ritter

Anilkumar Chandolu

Matthew J King

Yongjun Jeff Hu

Haitao Liu

Jordan D Greenlee

Lifang Xu

Richard J Hill

Daniel Billingsley

Harsh Narendrakumar Jain

S M Istiaque Hossain

Kar Wui Thong

Tom George

Amritesh Rai

Yoshiaki Fukuzumi

Paolo Tessariol

Indra V Chary

Jun Fujiki

Shuangqiang Luo

Kunal Shrotri

Shuji Tanaka

David Ross Economy

Umberto Maria Meotto

Andrew Li

Matthew Holland

Kye Hyun Baek

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. The channel-material strings directly electrically couple to conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises a laterally-outer insulative lining extending longitudinally-along the immediately-laterally-adjacent memory-blocks. The laterally-outer insulative lining has its lowest surface between a top and a bottom of the lowest conductive tier. The laterally-outer insulative lining has its highest surface at or below a lowest surface of the next-lowest conductive tier. Laterally-inner insulating material extends longitudinally-along the immediately-laterally-adjacent memory blocks laterally-inward of the laterally-outer insulative lining. An interface is between the laterally-outer insulative lining and the laterally-inner insulating material. Methods are also disclosed.

Memory circuitry and method used in forming memory circuitry

Some embodiments include an integrated assembly having a channel-material-pillar extending vertically through a stack of alternating conductive levels and insulative levels. The channel-material-pillar includes a first semiconductor material. A second semiconductor material is directly against an upper region of the channel-material-pillar. The second semiconductor material has a higher dopant concentration than the first semiconductor material and joins to the first semiconductor along an abrupt interfacial region such that there is little to no mixing of dopant from the second semiconductor material into the first semiconductor material. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.

Microelectronic devices comprising stack structures having pillars and elliptical conductive contacts

A microelectronic device, including a stack structure including alternating conductive structures and dielectric structures is disclosed. Memory pillars extend through the stack structure. Contacts are laterally adjacent to the memory pillars and extending through the stack structure. The contacts including active contacts and support contacts. The active contacts including a liner and a conductive material. The support contacts including the liner and a dielectric material. The conductive material of the active contacts is in electrical communication with the memory pillars. Methods and electronic systems are also disclosed.

Microelectronic devices including active contacts and support contacts, and related electronic systems and methods

An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures overlying a source tier, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprise a channel material extending vertically through the stack. The electronic device comprises an additional stack overlying the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, and pillars extending through the additional stack and overlying the strings of memory cells. Each of the pillars is horizontally offset in a first horizontal direction and in a second horizontal direction transverse to the first horizontal direction from a center of a corresponding string of memory cells. The electronic device comprises conductive lines overlying the pillars, and interconnect structures directly contacting the pillars and the conductive lines. Related electronic devices, systems, and methods are also described.

Electronic devices including tiered stacks including conductive structures isolated by slot structures, and related systems and methods

A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

Microelectronic devices including conductive structures

A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.

Apparatuses including device structures including pillar structures

A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually electrically coupled to individual of the channel-material strings. Insulating material is laterally-between immediately-adjacent of the conductive vias. At least some of the insulating material is vertically removed to form an upwardly-open void-space that is circumferentially about multiple of the conductive vias. Insulative material is formed laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space. Digitlines are formed above that are individually electrically coupled to a plurality of individual of the conductive vias there-below. Other embodiments, including structure independent of method, are disclosed.

Memory array and method used in forming a memory array

Some embodiments include an integrated assembly having a supercapacitor supported by a semiconductor substrate. The supercapacitor includes first and second electrode bases. The first electrode base includes first laterally-projecting regions, and the second electrode base includes second laterally-projecting regions which are interdigitated with the first laterally-projecting regions. A distance between the first and second laterally-projecting regions is less than or equal to about 500 nm. Carbon nanotubes extend upwardly from the first and second electrode bases. The carbon nanotubes are configured as a first membrane structure associated with the first electrode base and as a second membrane structure associated with the second electrode base. Pseudocapacitive material is dispersed throughout the first and second membrane structures. Electrolyte material is within and between the first and second membrane structures. Some embodiments include methods of forming integrated assemblies.

Supercapacitors and integrated assemblies containing supercapacitors

A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.

Microelectronic devices including tiered stacks including conductive structures isolated by slot structures, and related electronic systems and methods

A microelectronic device comprises pillar structures comprising semiconductive material, contact structures in physical contact with upper portions of the pillar structures, and conductive structures over and in physical contact with the contact structures. Each of the conductive structures comprises a lower portion having a first horizontal width, an upper portion vertically overlying the lower portion and having a second horizontal width greater than the first horizontal width, and an additional portion vertically interposed between the lower portion and the upper portion and having arcuate horizontal boundaries defining additional horizontal widths varying from the first horizontal width proximate the lower portion to a relatively larger horizontal width proximate the upper portion. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems

An electronic device comprises a stack structure comprising vertically alternating insulative structures and conductive structures arranged in tiers, pillars extending vertically through the stack structure, and a barrier material overlying the stack structure. The electronic device comprises a first insulative material extending through the barrier material and into an upper tier portion of the stack structure, and a second insulative material laterally adjacent to the first insulative material and laterally adjacent to at least some of the conductive structures in the upper tier portion of the stack structure. At least a portion of the second insulative material is in vertical alignment with the barrier material. Additional electronic devices and related methods and systems are also disclosed.

Growing community of inventors

Boise, ID, United States of America

Sidhartha Gupta