Sandisk Technologies Inc.

Siddhesh Darne

Venkatesh Ramachandra

Tianyu Tang

Grishma Shah

Julian Vlaiko

Dmitry Vaysman

Hanan Borukhov

George Kakuru

Venky Ramachandra

Aspects of a storage device including a memory and a controller are provided, which allow for error detection or data integrity checking during data transfer of write operations and read operations. The controller may be configured to generate data integrity information based on at least one data byte to be written to the memory, and to transfer the at least one data byte contemporaneously with the data integrity information on separate data paths to the memory. The controller may be configured to select between transferring data bus inversion information or the data integrity information based on whether a data integrity protection mode is active between the memory and the controller. The memory may be configured to receive the at least one data byte and the data integrity information from the controller, and detect whether an error exists in the at least one data byte based on the data integrity information.

Toggle mode interface for data integrity protection

In a non-volatile memory device, the amount of delay along an I/O path for transferring received data to a sense amplifier and the amount of delay along a clock path to the sense amplifier can differ. To compensate for this differential delay, a replica of each of the I/O path and the clock path can be included on the memory device. The replica circuits can be used to determine this differential delay between the two paths. To compensate for this difference, an additional delay can be introduced into one or both of the paths, such as in the I/O path, so that any difference in propagations times can be reduced.

Data path oscillator mismatch error reduction for non-volatile memory

The disclosure provides circuits and methods for increasing NAND input/output (I/O) bandwidth during read/write operations. The method includes transmitting a clock signal between a controller I/O circuit and a memory I/O circuit along a read enable bus, transmitting 8 bits of data along an I/O bus, and transmitting 2 bits of data along a data strobe signal (DQS) bus. Transmitting 2 bits of data along the DQS bus includes transmitting a first DQS data signal along the DQS bus and transmitting a first inverse DQS data signal along the DQS bus.

NAND IO bandwidth increase

A command/address sequence associated with a read/write operation for a memory device utilizes various existing command/address clock signals in a novel way that obviates the need to utilize the I/O bus. As such, the command/address sequence can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence encodes bit information on first and second enable signals and utilizes rising or falling edges of a clock signal to latch the encoded bit information, which can then be decoded to determine corresponding command and address codes. A chip select sequence is also disclosed that enables a memory chip configuration to be employed in which each chip in a package shares a common connection to a controller but does not require hard-coded pins for performing chip select.

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Milpitas, CA, United States of America

Siddhesh Darne