Synopsys, Inc.

Siddhartha Nath

Vishal Khandelwal

Wei-Ting Chan

Ravi Mamidi

Sudipto Kundu

Praveen Ghanta

Yi-Chen Lu

A graph-based timing analysis (GBA) is applied to a circuit design that includes a routed gate-level netlist to produce timing estimates of the circuit design. A machine learning (ML) model is applied to modify these GBA timing estimates of the circuit design to make them more accurate. For example, the ML model may be trained using timing estimates from path-based timing analysis as the ground truth, and using features of the circuit design from the GBA as input to the ML model.

Machine learning-enabled estimation of path-based timing analysis based on graph-based timing analysis

When designing circuits to meet certain constraint requirements, it is challenging to determine whether a given circuit design will meet the constraints. A designer at an early stage of the circuit design (e.g., synthesis or placement) may have limited information to rely on in order to determine whether the eventual circuit, or some design variation thereof, will satisfy those constraints without fully designing the circuit. The approaches described herein use a machine learning (ML) model to predict, based on features of partial circuit designs at early stages of the design flow, whether the full circuit is likely to meet the constraints. Additionally, the disclosed approaches allow for the ranking of various circuit designs or design implementations to determine best candidates to proceed with the full design.

Machine learning-based prediction of metrics at early-stage circuit design

Systems and methods for adjusting a digital circuit design are described. For example, the method may include selecting a first path in the digital circuit design. The first path includes a plurality of gates. The method also includes generating a k-hop neighborhood graph of the first path, encoding the k-hop neighborhood graph into a state vector, and applying a machine learning model to the state vector to determine an adjustment to be made on a first gate of the plurality of gates. The method further includes changing the first gate based on the adjustment.

Reinforcement learning-based adjustment of digital circuits

A machine learning (ML) system is trained to predict the number of design rules violations of a circuit design that includes a multitude of Gcells. To achieve this, a netlist associated with the circuit design is placed by a place and route tool. A first list of features associated with the placed netlist is delivered to the ML system. A global route of the circuit design is performed by a global router. Next, a second list of features is delivered from the global router to the ML system. Thereafter, a detailed route of the circuit design is performed by a detailed router. A label associated with each Gcell in the circuit design is delivered to the ML system from the detailed route. The ML system is trained using the first and second list of features and the labels.

Machine learning-based algorithm to accurately predict detail-route DRVS for efficient design closure at advanced technology nodes

Training data is collected for each training integrated circuit (IC) design of a set of training IC designs by: extracting a first set of IC design features in a first stage of an IC design flow, and extracting a first set of IC design labels in a second stage of the IC design flow, where the first stage of the IC design flow occurs earlier than the second stage of the IC design flow in the IC design flow. Next, a machine learning model is trained based on the training data.

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Santa Clara, CA, United States of America

Siddhartha Nath