Seagate Technology Incorporated

Avago Technologies General IP (singapore) Pte. Ltd.

Intel Corporation

Siddhartha Kumar Panda

Mark Ish

Kunal Sablok

Ryan James Goss

Sujoy Sen

Horia Cristian Simionescu

Shashank Nemawarkar

Balakrishnan Sundararaman

Kapil Sundrani

Daniel John Benjamin

Ryan Charles Weidemann

Durga Prasad Bhattarai

Ramkumar Venkatachalam

Dileep Kumar Sharma

Bagavathy Raj Arunachalam

Jayaraj Puthenpurackal Rajappan

Technologies for quality of service (QoS) management include a computing device having a physical storage volume and multiple processor cores. A management thread reads I/O counters that are each associated with a logical volume and a processor core. The logical volumes are backed by the physical storage volume. The management thread configures stop bits as a function of the I/O counters and multiple QoS parameters. Each stop bit is associated with a logical volume and a processor core. The QoS parameters include minimum guaranteed bandwidth and optional maximum allowed bandwidth for each logical volume. A worker thread reads the stop bit associated with a logical volume and a processor core, accesses the logical volume if the stop bit is not set, and updates the I/O counter associated with the logical volume and the processor core in response to accessing the logical volume. Other embodiments are described and claimed.

Technologies for lockless, scalable, and adaptive storage quality of service

A method operable with the storage device includes determining a workload to the storage device based on host Input/Output (I/O) requests to the storage device. When the workload is above a threshold, a first portion of the storage device is selected for garbage collection based on the I/O requests. Otherwise, when the workload is below the threshold, a second different portion of the storage device is selected for garbage collection based on a storage ability of the second portion of the storage device.

Garbage collection of a storage device

Method and apparatus for asynchronous discovery of processing and storage nodes coupled via an expander switch in a fabric. In some embodiments, an initiator device operates as a processing node to transfer data to and from a non-volatile memory (NVM) of a target device at a storage node. One of the initiator or target devices is activated prior to the other device. The second activated device broadcasts a discovery command responsive to the activation of the second activated device and prior to receipt of a request for the discovery command from the first activated device. The first activated device processes the discovery command to establish an I/O communication link between the first activated device and the second activated device. The discovery command may include a non-volatile memory express (NVMe) controller list, and the NVM may be arranged as one or more NVMe namespaces.

Asynchronous discovery of initiators and targets in a storage fabric

The disclosed technology provides for selection of a subset of available non-volatile memory devices in an array to receive a dirty cache data of a volatile cache responsive to detection of a power failure. In one implementation, the selection of the non-volatile memory devices is based on one or more predictive power parameters usable to estimate a time remaining during which a reserve power supply can support a cache offload to the selected subset of devices.

Cache offload based on predictive power parameter

A storage controller coupled to a host computer is dynamically configured by a device driver executing in the host computer. The storage controller manages a logical volume for the host using a set of flash-based storage devices arranged as a redundant array of inexpensive disks (RAID). The device driver identifies a RAID type for the logical volume and a queue depth from a stream of I/O commands. For a logical volume in RAID 0, the device driver compares the queue depth to a threshold value and configures the storage controller to process the stream of I/O commands with a first path or an alternative path based on a result of the comparison. For a logical volume in RAID 5, the device driver performs a similar comparison and uses the result to direct the storage controller to use a write back or a write through mode of operation.

Device driver, method and computer-readable medium for dynamically configuring a storage controller based on RAID type, data alignment with a characteristic of storage elements and queue depth in a cache

An apparatus having a memory circuit and a manager is disclosed. The memory circuit generally has (i) one or more Flash memories and (ii) a memory space that spans a plurality of memory addresses. The manager may be configured to (i) receive data items in a random order from one or more applications, (ii) write the data items in an active one of a plurality of regions in a memory circuit and (iii) mark the memory addresses in the active region that store the data items as used. Each data item generally has a respective host address. The applications may be executed in one or more computers. The memory addresses in the active region may be accessed in a sequential order while writing the data items to minimize a write amplification. The random order is generally preserved between the data items while writing in the active region.

Reducing write amplification in a flash memory

Growing community of inventors

Bengaluru, India

Siddhartha Kumar Panda