Agere Systems Guardian Corp.

Agere Systems Inc.

Lucent Technologies Inc.

Siddhartha Bhowmik

Sailesh Mansinh Merchant

Pradip Kumar Roy

Sidhartha Sen

Sailesh Chittipeddi

Joseph William Buckfeller

Frank Minardi

Minseok Oh

Darrell L Simpson

G Craig Clabough

Steven Mark Anderson

An interconnect structure of a semiconductor device includes a tungsten plug () deposited in a via or contact window (). A barrier layer () separates the tungsten plug () from the surface of a dielectric material () within which the contact window or via () is formed. The barrier layer () is a composite of at least two films. The first film formed on the surface of the dielectric material () within the via () is a tungsten silicide film (). The second film is a tungsten film () formed on the tungsten silicide film (). A tungsten plug () is formed on the tungsten film () to complete interconnect structure. The barrier layer () is deposited using a sputtering technique performed in a deposition chamber. The chamber includes tungsten silicide target () from which the tungsten silicide film () is deposited, and a tungsten coil () from which the tungsten film () is deposited.

Barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer

A system and method for eliminating interconnect extrusions in vias that are formed during ionized metal plasma processing. By eliminating interconnect extrusions in vias, reliability failures and yield loss are decreased. The extrusions of interconnect metallization occur while wafers are subject to elevated temperatures that cause the internal stresses in the interconnect metallization to transit from a substantially tensile mode to a substantially compressive mode. By controlling the interconnect temperature to be below the temperature at which the interconnect transits from a tensile to a compressive mode, interconnect extrusions in vias are eliminated. The interconnect temperature is controlled by using an actively cooled pedestal in combination with a low temperature IMP deposition process. In addition, the IMP processing time may also be decreased to limit heating of the interconnect.

Method and system for eliminating extrusions in semiconductor vias

The present invention provides a method of depositing a film on a surface of a coil that includes depositing a metal from a target onto a surface of a coil to form a first film on the surface and forming a second film over the first film at a low pressure and at a first power at the target that is substantially higher than a first power at the component's surface. The conditioned deposition tool is well suited for manufacturing integrated circuits.

Method of coil preparation for ionized metal plasma process and method of manufacturing integrated circuits

The present invention provides a method of forming a metal oxide metal (MOM)capacitor on a substrate, such as a silicon substrate, of a semiconductor wafer in a rapid thermal process (RTP) machine. The MOM capacitor is fabricated by forming a metal layer on the semiconductor substrate. The metal layer is then subjected to a first rapid thermal process in a substantially inert but nitrogen-free atmosphere that consumes a portion of the metal layer to form a first metal electrode layer and a silicide layer between the first metal electrode and the semiconductor substrate. The semiconductor wafer is then subjected to a second rapid thermal process. During this process, the remaining portion of the metal layer is oxidized to form a metal oxide on the first metal electrode, which serves as the dielectric layer of the MOM capacitor. Following the formation of the dielectric layer, a second metal electrode layer is then conventionally formed on the metal oxide, which completes the formation of the MOM capacitor. Preferably, the first electrode layer and the metal oxide layer are formed in a single RTP machine.

Method of forming metal oxide metal capacitors using multi-step rapid material thermal process and a device formed thereby

The invention includes a process for copper metallization of an integrated circuit, comprising the steps of forming tantalum on a substrate, forming tantalum nitride over the tantalum, forming titanium nitride over the tantalum nitride, forming copper over the titanium nitride and integrated circuits made thereby. The invention is particularly useful in forming damascene structures with large aspect ratios.

Barrier for copper metallization

A titanium-tantalum barrier layer film for use in conjunction with an interconnect film such as copper and a method for forming the same provides a relatively titanium rich/tantalum deficient portion adjacent the interface it forms with a dielectric film and a relatively tantalum rich/titanium deficient portion adjacent the interface it forms with a conductive interconnect film formed over the barrier layer film. The titanium rich/tantalum deficient portion provides good adhesion to the dielectric film and the tantalum rich/titanium deficient portion forms a hetero-epitaxial interface with the interconnect film and suppresses the formation of inter-metallic compounds. A single titanium-tantalum film having a composition gradient from top-to-bottom may be formed using various techniques including PVD, CVD, sputter deposition using a sputtering target of homogeneous composition, and sputter deposition using multiple sputtering targets. A composite titanium-tantalum film consists of two separately formed films.

Titanium-tantalum barrier layer film and method for forming the same

The present invention provides a method of forming a metal oxide metal (MOM) capacitor on a substrate, such as a silicon substrate, of a semiconductor wafer in a rapid thermal process (RTP) machine. The MOM capacitor is fabricated by forming a metal layer on the semiconductor substrate. The metal layer is then subjected to a first rapid thermal process in a substantially inert but nitrogen-free atmosphere that consumes a portion of the metal layer to form a first metal electrode layer and a silicide layer between the first metal electrode and the semiconductor substrate. The semiconductor wafer is then subjected to a second rapid thermal process. During this process, the remaining portion of the metal layer is oxidized to form a metal oxide on the first metal electrode, which serves as the dielectric layer of the MOM capacitor. Following the formation of the dielectric layer, a second metal electrode layer is then conventionally formed on the metal oxide, which completes the formation of the MOM capacitor. Preferably, the first electrode layer and the metal oxide layer are formed in a single RTP machine.

Method of forming metal oxide metal capacitors using multi-step rapid thermal process and a device formed thereby

A method is for cleaning via openings during manufacturing of integrated circuits. The method preferably comprises the steps of sputter cleaning the via opening at least once, and exposing the via opening to a reducing atmosphere at least once. The method may include alternatingly repeating the sputter cleaning and exposing steps. The step of sputter cleaning is preferably performed prior to the step of exposing, and a sputter cleaning may be performed after a last step of exposing the via opening to the reducing atmosphere. In one embodiment, the exposed metal portion comprises a metal compound, such as an oxide. Accordingly, the step of sputter cleaning removes at least a portion of the metal oxide, and the step of exposing comprises reducing at least a portion of the metal oxide. The invention is particularly applicable when the metal interconnection layer is a copper, as copper readily oxides at its exposed surface.

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Orlando, FL, United States of America

Siddhartha Bhowmik