Stmicroelectronics International N.v.

Stmicroelectronics Pvt. Ltd.

Siddharth Gupta

Nitin Jain

Anand Kumar Mishra

Dibya Dipti

Rakesh Kumar Sinha

Vamsi Krishna Gullapalli

A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains.

Signal synchronization in multi-voltage domains

A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Write circuitry for hierarchical memory architectures

Write circuitry for hierarchical memory architecture

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Siddharth Gupta