Qualcomm Incorporated

Siddesh Halavarthi Math Revana

Kaustav Roychowdhury

Darshan Kumar Nandanwar

Raghavendra Srinivas

Nilesh Dhavlikar

Kuldeep Singh Chahal

Srinivasa Kumar Munivenkata Gowda

Small timing margins between the period of a clock and the propagation delays of critical signal paths in an IC at a given supply voltage create a risk for errors in response to voltage droop. Increasing the supply voltage increases the timing margin but also increases power consumption. A margin management circuit includes a delay path having a configurable delay that corresponds to the propagation delay of a critical signal path. Based on a detected timing margin of the delay path, a frequency adjustment signal is generated to adjust the clock frequency to adjust the timing margin. In response to a reduction in the timing margin, due to a sudden voltage droop, the clock frequency may be adjusted to avoid errors. In some examples, the frequency of the clock is compared to a desired frequency and the supply voltage is adjusted to restore the desired frequency.

Power saving circuits to adjust frequency according to dynamic timing margin changes and adjust supply voltage to restore desired frequency and related methods

Providing interrupt service routine (ISR) prefetching in multicore processor-based systems is disclosed. In one aspect, a multicore processor-based system provides an ISR prefetch control circuit communicatively coupled to an interrupt controller and a plurality of instruction fetch units (IFUs) of a corresponding plurality of processor elements (PEs). Upon receiving an interrupt directed to a target PE of the plurality of PEs, the interrupt controller provides an interrupt request (IRQ) identifier to the ISR prefetch control circuit. Based on the IRQ identifier, the ISR prefetch control circuit fetches an ISR pointer to an ISR corresponding to the IRQ identifier. The ISR prefetch control circuit next selects a prefetch PE of the plurality of PEs to perform a prefetch operation to retrieve the ISR on behalf of the target PE, and provides an ISR prefetch request, including the ISR pointer, to an IFU of the prefetch PE.

Providing interrupt service routine (ISR) prefetching in multicore processor-based systems

Providing private cache allocation for power-collapsed processor cores in processor-based systems is provided. In one aspect, a processor-based system provides multiple processor cores, each residing within its own processor core power domain. Each processor core is provided with a private cache residing within its own private cache power domain, configured to be power-controlled independently of the corresponding processor core power domain. When a first processor core is placed in a power-collapsed state, a snoop controller corresponding to the private cache of the first processor core maintains power to the private cache power domain of the private cache, allowing the private cache to remain online. The snoop controller also enables allocation and snooping of the private cache by a second processor core while the first processor core remains in the power-collapsed state. In this manner, each private cache may be used for data-caching operations while its corresponding processor core is power-collapsed.

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Bengaluru, India

Siddesh Halavarthi Math Revana