Avago Technologies General IP (Singapore) Pte. Ltd.

Siddartha Kumar Panda

Horia Cristian Simionescu

Kunal Sablok

Veera Kumar Reddy Oleti

An apparatus having a cache and a circuit is disclosed. The cache includes a plurality of cache lines. The cache is configured to (i) store a plurality of data items in the cache lines and (ii) generate a map that indicates a dirty state or a clean state of each of the cache lines. The cache also has a write-back policy to a memory. The circuit is configured to (i) check a location in the map corresponding to a read address of a read request and (ii) obtain read data directly from the memory by bypassing the cache in response to the location having the clean state.

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Bengaluru, India

Siddartha Kumar Panda