Intel Corporation

Siang Yeong Tan

Wee Hoe

Min Suet Lim

Tin Poay Chuah

Chee Lim Nge

Chia-Hung Sophia Kuo

Zhongsheng Wang

Samantha Rao

Mooi Ling Chang

Fern Nee Tan

Chee Chun Yee

Chan Kim Lee

Say Thong Tony Tan

Somvir Singh Dahiya

Tai Loong Wong

A first circuit to receive from a sensor a thermal condition of a voltage regulator while circuitry comprising the voltage regulator is to regulate delivery of power to a power domain having first and second components. The circuitry is to control a first power consumption rate of the first component based on a first parameter and control a second power consumption rate of the second component based on a second parameter. The first circuit monitors the thermal condition and generates an evaluation result based on a test criterion. A second circuit receives from the first circuit a signal based on the evaluation result. Based on the signal, the second circuit is to signal the circuitry to change the first parameter. An amount of any change to the second parameter based on the evaluation result is different than an amount of change to the first parameter based on the evaluation result.

Thermally optimized power delivery

The present disclosure generally relates to a scalable computer circuit board having a first power level semiconductor package coupled to at least one base-level voltage regulator module, which is coupled to a plurality of connection receptacles that are configured for connecting with a voltage regulator module positioned on a second level, as a standardized base unit. To scale the base unit, a second power level semiconductor package may be exchanged for the first power level semiconductor package in conjunction with one or more voltage regulator module board being positioned over a corresponding number of base-level voltage regulator modules and coupled to their plurality of connection receptacles.

Stacked scalable voltage regulator module for platform area miniaturization

A semiconductor device and associated methods are disclosed. In one example, a processor die is coupled to a first side of a package substrate, and a memory die coupled to a second side of the package substrate. A system accelerator die is further coupled to the package substrate. In selected examples, the system accelerator die provides performance improvements, such as higher cached memory speed and/or higher memory bandwidth.

Compact semiconductor chip system and method

Techniques for serial interface charging are described. An apparatus may comprise, for example, a serial interface such as a thunderbolt interface and a charger control circuit coupled to the serial interface, the charger control circuit arranged to operate in a charging mode or an on-the-go (OTG) mode based on information received from the serial interface. Another apparatus may comprise, for example, a serial interface such as a thunderbolt interface and a charger circuit coupled to the serial interface, the charger circuit arranged to operate in a first charging mode or a second charging mode based on information received from the serial interface, the information comprising characteristics of a device coupled to the serial interface. Other embodiments are described and claimed.

Techniques for serial interface charging

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Bayan Lepas, Malaysia

Siang Yeong Tan