Compaq Computer Corporation, Inc.

Microsoft Technology Licensing, LLC

Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Compaq Information Technologies Group, L.p.

Hewlett-packard Development, L.p.

Siamak Tavallaei

Cullen Edwin Bash

John P Franz

Joseph P Miller

Robert A Lester

John Edward Larson

John MacLaren

Christian H Post

Jeffrey S Autor

Theodore F Emerson

Gregg Bernard Lesartre

Tahir Cader

Ishwar Agarwal

George D Megason

Paul A Santeler

John S Lacombe

Brett D Roscoe

Paul R Culley

John Grant Bennett

Gary J Piccirillo

Jerome J Johnson

Gary B Kotzur

Chanh V Hua

Patrick Lee Ferguson

Darren John Cepulis

David F Heinrich

Russ William Herrell

Alan L Goodrum

Lidia Warnes

Robert C Elliott

Jeffery L Galloway

Tim W Majni

Eric Rose

Anisha Anand

Vishal Soni

Louis R Gagliardi

John V Butler

Daniel Stuart Hull

Brian S Hausauer

Benjamin H Clark

Eric E Rose

Dan Fink

An T Vu

Thomas T Hardt

Yoocharn Jeon

Dwight L Barron

Brian T Purcell

Raphael Gay

John W Butler

Harvey White, Jr

Alexander C Ekrot

Niru Kumari

Jose A Santin

Robert F Olson

Bret D Roscoe

Gordon R Clark

David B Fujii

Sergio Escobar-Vargas

Elizabeth A Richard

Brian Humpherys

Doron Chosnek

Wade D Vinson

James A Mouton

Barry P Basile

Brain S Hausauer

Sarah Anthony

Matthew Schumacher

George H Myers

Kevin Nguyen

Binh Quang Nguyen

Joseph E Foster

A computing device includes a system-on-a-chip. The computing device comprises a network interface controller (NIC) that hosts a plurality of virtual functions and physical functions. Two or more compute nodes are coupled to the NIC. Each compute node is configured to operate a plurality of Virtual Machines (VMs). Each VM is configured to operate in conjunction with a virtual function via a virtual function driver. A dedicated VM operates in conjunction with a virtual NIC using a physical function hosted by the NIC via a physical function driver hosted by the compute node. The computing device further comprises a fabric manager configured to own a physical function of the NIC, to bind virtual functions hosted by the NIC to individual compute nodes, and to pool I/O devices across the two or more compute nodes.

Computing device with independently coherent nodes

A method for memory address mapping in a disaggregated memory system includes receiving an indication of one or more ranges of host physical addresses (HPAs) from a compute node of a plurality of compute nodes, the one or more ranges of HPAs including a plurality of memory addresses corresponding to different allocation slices of the disaggregated memory pool that are allocated to the compute node. The one or more ranges of HPAs are converted into a contiguous range of device physical addresses (DPAs). For each DPA, a target address decoder (TAD) is identified based on a slice identifier and a slice-to-TAD index. Each DPA is mapped to a media-specific physical element of a physical memory unit of the disaggregated memory pool based on the TAD.

Addressing for disaggregated memory pool

Disclosed herein is a thin-provisioned multi-node computer system with a disaggregated memory pool and a pooled memory controller. The disaggregated memory pool is configured to make a shared memory capacity available to each of a plurality of compute nodes, such memory capacity being thinly provisioned relative to the plurality of compute nodes. The pooled memory controller is configured to assign a plurality of memory segments of the disaggregated memory pool to the plurality of compute nodes; identify a subset of the plurality of segments as cold segments, such identification being based on determining that a usage characteristic for each such cold segment is below a threshold; and page one or more of the cold segments out to an expanded bulk memory device, thereby freeing one or more assigned memory segments of the disaggregated memory pool.

Paging in thin-provisioned disaggregated memory

Examples are disclosed that relate to a disaggregated memory pool. One example provides a memory system comprising a memory controller and memory attached to the memory controller and forming at least a portion of a disaggregated memory pool, the disaggregated memory pool including a plurality of slices that are each dynamically assigned to a respective compute node. The memory system is configured to receive a request to adjust an assignment of the memory pool to a requesting compute node, where the portion of the memory pool includes an unassigned slice that can satisfy the request, assign at least part of the unassigned portion to the requesting compute node, and where the portion of the memory pool does not include an unassigned slice that can satisfy the request, cause a request to be directed to another compute node to free at least one slice to the such compute node.

Disaggregated memory pool assignment

In some examples, performance counters for computer memory may include ascertaining a request associated with a memory address range of computer memory. The memory address range may be assigned to a specified performance tier of a plurality of specified performance tiers. A performance value associated with a performance attribute of the memory address range may be ascertained, and based on the ascertained performance value, a weight value may be determined. Based on the ascertained request and the determined weight value, a count value associated with a counter associated with the memory address range may be incremented. Based on an analysis of the count value associated with the counter, a determination may be made as to whether the memory address range is to be assigned to a different specified performance tier of the plurality of specified performance tiers. Based on a determination that the memory address range is to be assigned to the different specified performance tier, the memory address range may be assigned to the specified different performance tier.

Performance counters for computer memory

A computing device comprises two or more compute nodes, that each include two or more processor cores. Each compute node comprises an independently coherent domain that is not coherent with other compute nodes. A central IO die is communicatively coupled to each of the two or more compute nodes. A plurality of natively-attached volatile memory units are attached to the central IO die via one or more memory controllers. The central IO die includes one or more home agents for each compute node. The home agents are configured to map memory access requests received from the compute nodes to one or more addresses within the natively attached volatile memory units.

A method for rendering data invalid within a memory array is described. The method includes establishing governing metadata for a memory location within a memory array. The method also includes receiving a request to retrieve data from the memory location. The method also includes determining whether color metadata associated with the data matches the governing metadata. The method also includes returning the data when the color metadata matches the governing metadata. The method also includes returning invalidated data when the color metadata does not match the governing metadata.

Rendering data invalid in a memory array

A printed circuit board with a two-dimensional torus topology provided herein. The printed circuit board includes an array of board connectors, an input port and an output port, and a set of interconnections. Each board connector of the array of board connectors is formed to receive an electronic connector. The input port and the output port are formed on each board connector to provide an identical trace routing direction. The set of interconnections are formed to connect each board connector to another board connector. The signal path between each of the interconnections has a length less than a distance between a first board connector and a last board connector in the array of board connectors.

Two-dimensional torus topology

A multimodal memristor memory provides selectable or reconfigurable operation in a plurality of operational modes of a memristor. The multimodal memristor memory includes a memristor having a plurality of operational modes. The multimodal memristor memory further includes a reconfigurable interface driver to select an operational mode of the plurality of operational modes of the memristor. The memristor is to operate in the operational mode selected by the reconfigurable interface driver.

Multimodal memristor memory

A system includes off-memory-module ECC-supplemental memory. In a process, an ECC-capable memory controller converts non-ECC data words to ECC data words and distributes each ECC data word between a non-ECC memory module set (of one or more non-ECC memory modules) and the ECC-supplemental memory. A host computer system can include a baseboard on which are mounted an ECC-capable memory controller, off-memory-module ECC-supplemental memory, and sockets for installing non-ECC memory modules.

Off-memory-module ECC-supplemental memory system

Growing community of inventors

Spring, TX, United States of America

Siamak Tavallaei