Skyworks Solutions, Inc.

Applied Micro Circuits Corporation

Qualcomm Incorporated

Conexant Systems, Inc.

Siamak Fazelpour

Hassan S Hashemi

Ryan David Lane

Roberto Coccioli

Charles David Paynter

Mark Roger Patterson

Roberto U Villanueva

Mario Francisco Velez

Houssam Jomaa

Rajneesh Kumar

John A Loffink

Laxminarayan Sharma

Surasit Chungpaiboonpatana

Khosrow Golshan

Sun Yun

Priyatharshan Pathmanathan

Jean-Marc Papillon

Steven Jeffrey Martin

Michel Fleury

Jiantao Zheng

Surasit Chungpaibonnpatana

Some novel features pertain to a package substrate that includes a core layer, a first via, a first dielectric layer, and a first inductor. The core layer includes a first surface and a second surface. The first via is located in the core layer. The first dielectric layer is coupled to the first surface of the core layer. The first inductor is located in the first dielectric layer. The first inductor is coupled to the first via in the core layer. The first inductor is configured to generate a magnetic field that laterally traverses the package substrate. In some implementations, the package substrate further includes a first pad coupled to the first inductor, wherein the first pad is configured to couple to a solder ball. In some implementations, the package substrate includes a second via located in the core layer, and a second inductor located in the first dielectric layer.

Inductor embedded in a package substrate

A hybrid package having a processor module disposed on a substrate and an auxiliary module disposed on a patterned lid. The auxiliary module may be a memory module, a power management integrated circuit (PMIC) module, and/or other suitable module, that are located in the package along with the processor module. Having the auxiliary module in the package with the processor module reduces the noise at the solder bump between the processor module and the substrate. Having the auxiliary module in the package with the processor module also allows other modules to be added to the package without increasing the area of the package.

Power management integrated circuit (PMIC) integration into a processor package

The disclosure is related to pin layouts in a semiconductor package. One embodiment of the disclosure provides a rhombus shaped shared reference pin layout that isolates a set of differential pin pairs. The differential signal pin pairs are configured such that an axis formed by a vertical signal pin pair is orthogonal to and mutually bisecting an axis formed by a lateral signal pin pair.

Apparatus and methods for shielding differential signal pin pairs

Methods and apparatuses for reducing excess on die capacitance. The method couples a first die pad to a first via. The method couples a second die pad to a second via. The method couples a first inductor to the first die pad and the second via. The method couples a second inductor to the second die pad and the first via.

Highly coupled spiral planar inductors structure at bump to compensate on die excess capacitance of differential I/O

An interconnect via structure according to the present invention can be used to support high frequency broadband signal transmission. The interconnect vias progressively increase in size and pitch from the signal source layer of the package substrate to the terminal pad layer of the package substrate. Each interconnect via includes a plurality of conductive sections formed at different substrate layers. At each substrate layer, the size and pitch of the vias result in a specified impedance. In a practical embodiment, the via impedance at each substrate layer is constant (e.g., 50 ohms). The interconnect structure can maintain a constant impedance while transitioning from a relatively narrow pitch at the signal source layer to a relatively wide pitch at the terminal layer, which may correspond to the pitch of the package substrate solder balls.

Fanned out interconnect via structure for electronic package substrates

A passive component is realized on-die by fabricating a first conductor from either a layer of interconnect metal comprising copper or aluminum and being between approximately 1.0 micron and approximately 2.0 microns thick, or from a layer of under bump metal comprising either copper or aluminum and being between approximately 2.0 microns to approximately 5.0 microns thick. Following, a first isolation layer is formed over the first conductor. A second conductor having at least one external pad and comprising under bump metal is next fabricated over the first isolation layer. The second conductor can be fabricated substantially directly above the first conductor, for example. Thereafter, a second isolation layer having a hole over the external pad of the second conductor is formed over the second conductor. Subsequently, a bump attach site is fabricated at the hole in the second isolation layer over the external pad of the second conductor.

Method for integrating passives on-die utilizing under bump metal and related structure

An electronic package component includes a flip-chip device mounted to a BGA substrate. The BGA substrate includes conductive traces formed on its upper surface and configured in a coplanar waveguide structure. The package includes a dielectric coating applied over the conductive traces and over the upper surface of the substrate. The coating is formed from a material having a dielectric constant that is equal to or approximately equal to the dielectric constant of the BGA substrate material. The dielectric coating reduces the adverse effects caused by phase velocity dispersion of the signal propagated by the coplanar waveguide.

Electronic package substrate with an upper dielectric layer covering high speed signal traces

An electronic package, such as a ball grid array (&ldquo;BGA&rdquo;) package, includes a high speed signal trace formed at a conductive layer and a corresponding reference plane formed at another conductive layer. The reference plane includes a cutout region formed therein; the cutout region is positioned over the signal solder ball to which the high speed signal trace is coupled. The lateral center point of the cutout region is offset relative to the lateral center point of the signal solder ball. The offset configuration reduces the capacitance between the signal solder ball and the reference plane and improves the high frequency transmission characteristics of the electronic package.

Electronic package with offset reference plane cutout

In one embodiment, the invention includes first and second transmission lines fabricated in a redistribution layer over a semiconductor die. The first transmission line has a first distance from a first ground return path formed in a first metal level. The first transmission line has a first impedance corresponding to the first distance. In other words, the impedance of the first transmission line is affected by the distance between the first transmission line and the first ground return path. Similar to the first transmission line, the second transmission line has a second distance from a second ground return path formed in a second metal level. The second transmission line has a second impedance corresponding to the second distance. In other words, the impedance of the second transmission line is affected by the distance between the second transmission line and the second ground return path.

Controlled impedance transmission lines in a redistribution layer

An output of a voltage regulator is a core voltage line that runs adjacent to a die attach area on a packaging substrate. An input of the voltage regulator is typically coupled to a power supply which, in one embodiment, is also an I/O voltage line that runs adjacent to the die attach area. In one embodiment, the core voltage line is shaped as a ring encircling the die attach area on the packaging substrate. In another embodiment, the I/O voltage line is also shaped as a ring encircling the die attach area on the packaging substrate. Further, a semiconductor die having at least one I/O Vdd bond pad and at least one core Vdd bond pad can be mounted in the die attach area. The I/O Vdd bond pad and the core Vdd bond pad can be connected, respectively, to the I/O voltage ring and the core voltage ring.

Voltage regulation for semiconductor dies and related structure

An electronic device package includes a multilayer substrate having an interconnect structure configured to propagate a high frequency signal from one metal layer to another metal layer. The configuration and layout of the interconnect structure, particularly the arrangement of the reference vias associated with the signal via, is selected such that a desired filter response is achieved. The filter response is realized without any additional capacitor or inductor components. Thus, the natural discontinuity created by the vias and the inherent parasitic capacitance and inductance associated with the vias can be utilized to create a desired lowpass or bandpass filter response.

Package substrate interconnect layout for providing bandpass/lowpass filtering

According to one embodiment, a leadframe having at least one tab is placed inside a mold cavity. During the molding process, the ceiling of the mold cavity is pressed against the at least one tab, which in turn causes a bottom surface of the leadframe to be pressed firmly against a floor of the mold cavity. When a mold compound is injected into the mold cavity, the mold compound is prevented from reaching under the bottom surface of the leadframe. In one embodiment, the tabs are etched into one of the tie bars in the leadframe. The tabs are then mechanically formed at a nonzero angle with respect to a plane of a frame of the leadframe.

Exposed paddle leadframe for semiconductor die packaging

A transformer fabricated over a semiconductor die has been disclosed. A disclosed embodiment comprises a first inductor fabricated over a first bond pad. The first inductor is electrically connected to the first bond pad. For example, the bond pad can comprise copper, aluminum, copper-aluminum alloy, or gold. The disclosed embodiment further comprises a dielectric deposited over the first inductor. The disclosed embodiment further comprises a second inductor fabricated over the dielectric. For example, the dielectric can comprise BCB or low-k polyimide. Also, by way of example, the first and the second inductor can comprise copper, aluminum, copper-aluminum alloy, or gold.

Transformer comprising stacked inductors

One embodiment comprises a printed circuit board having a cavity. A leadframe having a leadframe paddle and at least one lead is situated with the cavity. A reference plane is situated within the printed circuit board at a predetermined distance below the at least one lead in a manner so as to result in a controlled impedance of the at least one lead. A total lead length of the at least one lead consists of an encased lead length and a free space lead length. By controlling the predetermined distance, the dielectric constant of the mold compound, the dielectric constant of the printed circuit board, the total lead length, the encased lead length, and the free space lead length of the at least one lead, the disclosed embodiment results in a controlled impedance of the at least one lead.

Controlled impedance leads in a leadframe for high frequency applications

An electronic device package includes a modified ball grid array (&ldquo;BGA&rdquo;) interconnect substrate upon which a flip-chip device is mounted. The flip-chip device includes one or more high speed input/output solder bumps corresponding to input/output signals having data rates of up to 40 Gbps. A high speed solder bump is directly connected to an interconnect via formed within the BGA substrate, and the via is directly connected to a respective BGA solder ball positioned at an interior point of the BGA solder ball matrix. The BGA substrate is void of BGA solder balls between the designated high speed BGA solder ball and at least one edge of the substrate, thus providing a clear path to the designated high speed BGA solder ball for a high speed conductive trace formed on a printed circuit board.

Growing community of inventors

San Diego, CA, United States of America

Siamak Fazelpour