Intergraph Corporation

Sun Microsystems, Inc.

Greenliant LLC

Other

Silicon Storage Technology, Inc.

Siamak Arya

Howard G Sachs

Fong-Long Lin

Dongsheng Xing

A memory controller, system and method for storing data blocks in a plurality of physically distinct non-volatile memory devices, each being independently written to or read from. The method includes generating one or more error checking data blocks based upon the plurality of data blocks; and storing the plurality of data blocks and the error checking data block(s) in the distinct physical non-volatile memory devices, with each data block in a different physical memory device. The method links the addresses of the data blocks and the error checking data block(s) in a cyclical link so that any entry to one of the data blocks will result in a link to all of the other data blocks. The memory controller has a processor and a memory for storing programming code for performing the foregoing method.

Method of storing blocks of data in a plurality of memory devices in a redundant manner, a memory controller and a memory system

A method of operating a controller for controlling the programming of a NAND memory chip is shown. The NAND memory chip has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum erasable unit. The method comprising storing in a temporary storage a first plurality of groups of data, wherein each of the groups of data is to be stored in a block of the NAND memory chip. Each group of data is indexed to the block with which it is to be stored. Finally, the groups of data associated with the same block are programmed into the same block in the same programming operation.

Method of writing to a NAND memory block based file system with log based buffering

An output buffer circuit for a non-volatile memory comprises an error check circuit, an error correction circuit, a switch circuit, and three storage circuits. The error check circuit receives the plurality of data bits and the plurality of ECC bits from the non-volatile memory to determine if the plurality of data bits need to be corrected and generates a correction signal. The error correction circuit receives the plurality of data bits and the plurality of ECC bits and generates a plurality of corrected data bits in response to the correction signal. A switch enables the output buffer circuit to concurrently performs operations of error check, error correction, and transfer of data bits out of the output buffer circuit on three distinct pluralities of data bits. The switch allows reallocation of storage circuits to different operations without any data transfer.

Dynamic buffer management in a NAND memory controller to minimize age related performance degradation due to error correction

A memory device comprises a non-volatile electrically alterable memory which is susceptible to read disturbance. The device has a control circuit for controlling the operation of the non-volatile memory. The device further has a first volatile cache memory. The first volatile cache memory is connected to the control circuit and is for storing data to be written to or read from the non-volatile memory, as cache for the memory device. The device further has a second volatile cache memory. The second volatile cache memory is connected to the control circuit and is for storing data read from the non-volatile memory as read cache for the memory device. Finally the control circuit reads data from the second volatile cache memory in the event of a data miss from the first volatile cache memory, and reads data from the non-volatile memory in the event of a data miss from the first and second volatile cache memories.

Memory device having read cache

A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

Instruction cache association crossbar switch

VLIW processor and method therefor

Instruction cache associative crossbar switch

An apparatus and method are described for implementing handling of exceptions caused by speculated instructions in a CPU having speculative execution capabilities. A CPU implementing speculative execution contains a speculative bit register file. Each speculative bit in the speculative bit register file is logically associated with a particular general purpose register, while remaining physically separate. This is accomplished through the use of a physically separate register file (the speculative bit register file) and register selection circuitry allowing simultaneous access to the two register files. The present invention provides instruction execution hardware supporting speculative execution with minimal impact on computational and structural complexity.

Method and apparatus for speculative execution of instructions

A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture efficiently executes software code by providing the processor with a grouper circuit which receives software code instructions from a secondary memory and groups these instructions based upon the content of the instructions and provides these grouped instructions to the instruction cache of the processor. In this processor, the old instruction software code conforms to an old instruction set which is a subset of the new instruction set. Such a system also functions where the processor maps instructions to itself

Processor architecture including grouping circuit

Apparatus and method for enabling substantially simultaneous access to consecutive entries in an addressable translation memory. The addressable translation memory may be either direct mapped or multi-way set associative. An address decoder receives input address signals and generates output select signals. Each input address signal and each output select signal corresponds to one of the registers in the translation memory. The invention includes a plurality of primary select lines, each of which transmits one of the output select signals to its corresponding register. The invention also includes a plurality of secondary select lines, each of which transmits an output select signal corresponding to a particular register to a second register, the particular register and the second register storing consecutive entries in the translation memory. The particular register and the second register receive the output select signal substantially simultaneously.

Method and apparatus for parallel access to consecutive TLB entries

A vector processor with a vector mask control unit provides an efficient approach for execution of conditional loops by a vector processor. The vector mask control unit includes respective vector masks for source and destination vector registers to specify the vector elements that should participate in the execution operation. Only the vector elements that correspond to active mask elements then participate in the execution operation, thus increasing the efficiency of the vector processor in executing conditional loops. Providing a vector mask control unit also allows the vector processor to perform a variety of functions more efficiently. For example, using a vector mask circuit allows a vector processor to efficiently perform vector reduction operations, neighboring vector operations and discrete fourier transform operations

Conditional vector processing

A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture, efficiently executes old software code by providing the processor with a compatibility circuit which receives old software code instructions from a secondary memory, groups these instructions according the new instruction set architecture and provides these grouped instructions to the instruction cache of the processor. In this processor, the old instruction software code conforms to an old instruction set which is a subset of the new instruction set.

Hardware compatibility circuit for a new processor architecture

A computing system is described in which groups of individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. During compilation of the instructions those which can be executed in parallel are identified. The system includes a register for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags and group identification tags indicative of the pipeline to which they should be dispatched, and the group of instructions which may be dispatched during the same operation. The pipeline and group identification tags are used to dispatch the appropriate groups of instructions simultaneously to the differing pipelines.

Growing community of inventors

Cupertino, CA, United States of America

Siamak Arya