Avalanche Technology, Inc.

Micron Technology Incorporated

Cirrus Logic Inc.

Lsi Corporation

Lexar Media, Inc.

Broadcom Corporation

Other

Netapp, Inc.

Round Rock Research, LLC

Promise Technology, Inc.

Siamack Nemazie

Mehdi Asnaashari

Petro Estakhri

Shiang-Jyh Chang

Anilkumar Mandapuram

Yu-Song Liao

Ngon Van Le

Jui-Yao Yang

Andrew Hyonil Chong

Ebrahim Abedifard

Young-Ta Wu

Mahmud M Assar

William R Foland, Jr

Kaushik L Popat

Balaji Venugopal Virajpet

Roger McPherson

Vineet Dujari

Maoxin Wei

Peter Sean Feeley

William Henry Radke

Parviz Keshtbod

John J Schadegg

Alan Chen

Berhanu Iman

Ruchirkumar Shah

William E Benson

Son H Ho

Michael George

Frederick Jaffin

Farshid Tabrizi

Ruchir Shah

Ronald Yamada

Dale P McNamara

Christopher P Zook

Senthil Kumar Chellamuthu

Jerrold Allen Beckmann

Ravishankar Tadepalli

Ahuja Gurmukhsingh Ramesh

Sam Nemazie

Mahmood Mozaffari

Anson Ba Phan

Jui-Yao (Ray) Yang

Edmond Sardariani

Raznik Karabed

Ronald M Yamada

Sunil Bhaskar Chaudhari

Jui-Yao (“Ray”) Yang

The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Memory controllers, memory systems, solid state drives and methods for processing a number of commands

A non-volatile memory device configured to emulate DRAM interface comprising a memory array that includes a plurality of magnetic memory cells organized into rows and columns with at least one row of the magnetic memory cells comprising one or more pages that store data during a burst write operation; a control circuit operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array.

Magnetic random access memory with dynamic random access memory (DRAM)-like interface

A non-volatile memory device configured to emulate DRAM interface comprising a memory array that includes a plurality of magnetic memory cells organized into rows and columns with at least one row of the magnetic memory cells comprising one or more pages that store data during a burst write operation; a control circuit; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array. The control circuit is operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; and after receiving one or more data units of the data by the memory array, allow a subsequent burst write or read command to begin before completion of the burst write operation in progress.

A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the one or more SSDs and creating a NVMe command structure for each sub-command.

Storage processor managing NVMe logically addressed solid state disk array

A memory device has a plurality of dedicated data blocks for storing user data and a plurality of dedicated overhead blocks for storing overhead data. A dedicated overhead block of the plurality of dedicated overhead blocks has a plurality of overhead segments. The overhead segments have physical block address registers configured to store physical block addresses defining respective dedicated data blocks.

Flash memory architecture with separate storage of overhead and user data

A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible.

High availability storage appliance

A storage system includes a central processing unit (CPU) subsystem including a CPU, a physically-addressed solid state disk (SSD) that is addressable using physical addresses associated with user data, provided by the CPU, to be stored in or retrieved from the physically-addressed SSD in blocks. Further, the storage system includes a non-volatile memory module, the non-volatile memory module having flash tables used to manage blocks in the physically addressed SSD, the flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. Additionally, the storage system includes a peripheral component interconnect express (PCIe) switch coupled to the CPU subsystem and a network interface controller coupled through a PCIe bus to the PCIe switch, wherein the flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption.

Storage system employing MRAM and array of solid state disks with integrated switch

A memory device configured to emulate DRAM comprising a memory array that includes a plurality of memory cells organized into rows and columns with at least one row of memory cells comprising one or more pages that store data during a burst write operation; a control circuit; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array. The control circuit is operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; and after receiving one or more data units of the data by the memory array, allow a subsequent burst write or read command to begin before completion of the burst write operation in progress.

The present invention is directed to a storage device including a storage media and a controller coupled thereto through a high speed interface. The storage media includes one or more byte-addressable persistent memory devices, one or more block-addressable persistent memory devices, a hybrid reserved area spanning at least a portion of the one or more byte-addressable persistent memory devices, and a hybrid user area spanning at least a portion of the one or more block-addressable persistent memory devices. The controller uses the hybrid reserved area to store private data. Each of the one or more byte-addressable persistent memory devices may include one or more magnetic random access memory (MRAM) arrays. Each of the one or more block-addressable persistent memory devices may include one or more NAND flash memory arrays. The high speed interface may be a universal flash storage (UFS) interface that operates in the full-duplex mode.

Management of memory array with magnetic random access memory (MRAM)

A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table.

Shared PCIe end point system including a PCIe switch and method for initializing the switch

A method of managing logical unit numbers (LUNs) in a storage system includes identifying one or more LUN logical block address (LBA)-groups being affected. The one or more LUN LBA-groups defining a LUN. The method further determining the existence of an association of each of the affected LUN LBA-groups to a portion of a storage pool and maintaining a mapping table to track the association of the LUN LBA-groups to the storage pool.

Method of LUN management in a solid state disk array

A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the SSDs independently of the command thereby causing striping across the SSDs.

Storage processor managing solid state disk array

In accordance with a method of the invention, host data, accompanied by host LBA, is received from a host. If the host data is determined not to be a duplicate host data, an available intermediate LBA (iLBA) is identified and the host LBA is linked to the identified iLBA. During writing of the received host data to the SSDs, an available SLBA is identified and saved to a table at a location indexed by the identified iLBA. Accordingly, the next time the same host data is received, it is recognized as a duplicate host data and the host address accompanying it is linked to the same iLBA, which is already associated with the same SLBA. Upon this recognition, an actual write to the SSDs is avoided.

Method and apparatus for de-duplication for solid state disks (SSDs)

A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.

Growing community of inventors

Los Altos Hills, CA, United States of America

Siamack Nemazie