Samsung Electronics Co., Ltd.

Seoul National University

Si-Young Choi

Byeong-Chan Lee

Deok-Hyung Lee

Yong-Hoon Son

In-Soo Jung

Jong-Wook Lee

Jong-Ryeol Yoo

Chul-Sung Kim

Tai-Su Park

Ki-Hyun Hwang

Jung-Woo Park

Myeong-Cheol Kim

Yu-Gyun Shin

Cheol Kyu Kim

Dong-Chan Kim

Jin-bum Kim

Seong-Hoon Jeong

Seung-Jae Baik

Jong-Hoon Kang

Jeong-Do Ryu

Jong-Ryol Ryu

Bo-un Yoon

Bon-Young Koo

Ho-young Kim

Byoung-ho Kwon

Yong-Joon Choi

Hong-suk Kim

Soo-jin Hong

Sun-Ghil Lee

Jin-Hwa Heo

Geum-jung Seong

Jae-Kwang Choi

Hee-Don Jeong

Se-jung Park

Bo-Kyeong Kang

Ji-Eun Han

Suk-Hoon Jeong

Dong-woon Shin

Jong-Ho Lee

Sung-Man Kim

Pil-Kyu Kang

Sang-Jin Hyun

Sun-Pil Youn

Ja-hum Ku

U-in Chung

Ki-hong Kim

Young-pil Kim

Ki-hyun Hwang

Deok-hyung Lee

Yong-Kug Bae

Jung-Min Ha

Sung-Kweon Baek

Jin-Tae Noh

Young-Jin Noh

Hyung-Ik Lee

Yong-Koo Kyoung

In-Sun Yi

Eui-Joon Yoon

Taek-Jung Kim

Gil-heyun Choi

Choong-Ho Lee

Sung-Min Kim

Byung-Lyul Park

Dong-Won Kim

Han-Mei Choi

Sang-Bom Kang

Jae-young Ahn

Seung-hwan Lee

Dongsoo Woo

Kyoung-hwan Yeo

Young-Pil Kim

Jong-Myeong Lee

Ji-soon Park

Dong-Kyu Lee

Hyung-Ho Lee

Seung-Hun Lee

Gab-Jin Nam

Chang-Won Lee

Sun-ghil Lee

Jong-Seo Hong

Sae-Woong Bahk

Sug-hun Hong

Dong-Woon Park

Seong-Jun Heo

Jong-Chan Shin

Sun-jung Kim

Young-Eun Lee

Si-Hyung Lee

Hyun-jong Lee

Sang-jin Hyun

Ji-Young Min

Sangbom Kang

Sang-Ryol Yang

Kwang-Min Park

Yi-Koan Hong

Bong-young Yoo

Heedon Hwang

Guk-hyon Yon

Jun-Kyu Cho

Il-Sup Kim

The present disclosure provides methods and apparatus relating to a 5G or pre-5G communication system for supporting a higher data rate than that of a 4G communication system, such as long term evolution (LTE). A method for processing traffic at a core network entity processes traffic includes transmitting a message for requesting assistance information to at least one base station, receiving the assistance information from the at least one base station, splitting the traffic based on the received assistance information, and transmitting the split traffic through a core network. A core network entity includes a transceiver and a processor configured to control the transceiver to transmit a message for requesting assistance information to at least one base station, receive the assistance information from the at least one base station, split traffic based on the received assistance information, and transmit data through the split traffic.

Method and apparatus for processing traffic in radio network system

Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Semiconductor device and method for fabricating the same

Provided is a semiconductor device. The semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an inter-layer insulating layer disposed on a second surface of the substrate, and a piezoelectric pattern formed between the metal pattern and the passivation layer on the first surface of the substrate. A through-silicon-via and/or a pad can be directly bonded to another through-silicon-via and/or another pad by applying pressure only, and without performing a heat process.

Semiconductor device having metal patterns and piezoelectric patterns

A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

Recessed channel array transistors, and semiconductor devices including a recessed channel array transistor

Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Methods of forming patterns of a semiconductor device

A method of forming a pattern includes forming a plurality of target patterns, forming a plurality of pitch violating patterns that make contact with the plurality of target patterns and are disposed between the plurality of target patterns, classifying the plurality of pitch violating patterns into a first region and a second region adjacent to the first region, and forming an initial pattern corresponding to one of the first region and the second region.

Method of forming pattern, reticle, and computer readable medium for storing program for forming pattern

In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.

Methods of forming recessed channel array transistors and methods of manufacturing semiconductor devices

A mask for forming patterns of a semiconductor device is provided. The mask includes first and second main patterns disposed to be spaced apart from each other about a cross point and extending in first and second directions different from each other, a third main pattern disposed spaced apart from the first and second main patterns while being disposed between the first and second main patterns so as to overlap the cross point, and at least one auxiliary pattern spaced apart from the third main pattern in the periphery of a portion of the third main pattern, which is not adjacent with the first and second main patterns.

Mask for forming patterns of semiconductor device

Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

Methods of forming integrated circuit devices having electrically conductive layers therein with partially nitridated sidewalls

A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.

Non-volatile memory devices with multiple layers having band gap relationships among the layers

A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

Semiconductor integrated circuit device and a method of fabricating the same

A flash memory device including a lower tunnel insulation layer on a substrate, an upper tunnel insulation layer on the lower tunnel insulation layer, and a P-type gate on the upper tunnel insulation layer, wherein the upper tunnel insulation layer includes an amorphous oxide layer.

Flash memory device including multilayer tunnel insulator and method of fabricating the same

Methods of manufacturing semiconductor devices may include forming a first layer on a first active region (P-channel FET), forming a second layer on a second active region (N-channel FET), the first and second layers including a silicon germanium (SiGe) epitaxial layer sequentially stacked on a silicon (Si) epitaxial layer, forming a first contact hole in an interlayer insulating film including a first lower region exposing the SiGe epitaxial layer of the first layer, forming a second contact hole in the interlayer insulating film including a second lower region penetrating through the SiGe epitaxial layer of the second layer and exposing the Si epitaxial layer of the second layer, forming a first metal silicide film including germanium (Ge) in the first lower region, forming a second metal silicide film not including Ge in the second lower region simultaneously with the forming of the first metal silicide film.

Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers

Growing community of inventors

Gyeonggi-do, South Korea

Si-Young Choi