Samsung Electronics Co., Ltd.

Si-Youn Kim

Yoo-Sang Hwang

In-Seak Hwang

Ki-Jae Hur

Hoon Jung

In one embodiment, a lower interlayer dielectric layer, and first and second landing pads penetrating the lower interlayer dielectric layer are formed on a substrate. Interconnection patterns covering the second landing pads are formed on the lower interlayer dielectric layer. An etch stop layer is formed over the interconnection patterns. An upper interlayer dielectric layer filling a gap region between the interconnection patterns is formed on the etch stop layer. The upper interlayer dielectric layer is patterned to form a preliminary contact hole between the interconnection patterns, where the etch stop layer is exposed at the bottom of the preliminary contact hole. The preliminary contact hole is extended and the etch stop layer exposed by the extended preliminary contact hole is removed to form a first contact hole exposing the first landing pad. A buried contact plug is then formed within the first contact hole.

Method of forming a semiconductor device having an etch stop layer and related device

According to various embodiments of the invention, there are provided line photo masks having a plurality of line patterns. These masks, which are suitable for preventing electric shorts between the data line images, are disposed on the semiconductor substrate by transferring them, which have the plurality of line patterns, onto a photoresist layer. One of the line patterns has at least one trench pattern.

Line photo masks and methods of forming semiconductor devices using the same

A semiconductor memory device includes a semiconductor substrate having an active region therein, an insulating layer on the substrate, and a lower electrode conductive pad extending through the insulating layer. The lower electrode conductive pad electrically contacts the active region at a lower surface of the lower electrode conductive pad. A lower electrode conductive plug on at least a portion of the lower electrode conductive pad electrically contacts the lower electrode conductive pad at an upper surface and at one sidewall thereof. The semiconductor device may further include a bitline conductor on the substrate adjacent the lower electrode conductive plug and an insulating spacer on a sidewall of the bitline conductor adjacent the lower electrode conductive plug. The insulating spacer may separate the lower electrode conductive plug from the bitline conductor by a distance sufficient to prevent electrical contact therebetween. Related methods are also discussed.

Methods of fabricating semiconductor memory devices including electrode contact structures having reduced contact resistance

To form a bottom electrode of a capacitor of a semiconductor device, a first insulation layer pattern having a first contact hole is formed on a substrate, and a contact plug for the bottom electrode is formed in the contact hole. A second insulation layer is formed on the first insulation layer pattern and the contact plug. The second insulation layer has a second etching rate higher than a first etching rate of the first insulation layer pattern. The second insulation layer is etched to form a second insulation layer pattern having a second a contact hole exposing the contact plug. A conductive film is formed on the sidewall and the bottom face of the second contact hole. According to the difference between the first etching rate and the second etching rate, the etching of the first insulation layer pattern near the contact plug is reduced.

Method of forming semiconductor device capacitor bottom electrode having cylindrical shape

Cylindrical capacitors and methods of fabricating the same are provided. The cylindrical capacitor includes a cylindrical storage node stacked on a semiconductor substrate. The cylindrical storage node has a base and a stepped sidewall located on the base. The stepped sidewall has at least two sub-sidewalls, which are sequentially stacked, and at least one joint portion that connects a lower sidewall of the sub-sidewalls to an upper sidewall stacked on the lower sidewall. An upper diameter of the respective sub-sidewalls is greater than a lower diameter thereof. Also, the upper diameter of the lower sidewall is greater than the lower diameter of the upper sidewall stacked on the lower sidewall. The method of fabricating the cylindrical storage node having a stepped sidewall includes sequentially forming a plurality of molding layers over a semiconductor substrate. An etch rate of a lower molding layer of the plurality of molding layers being faster than that of an upper molding layer on the lower molding layer with respect to a predetermined etchant. The plurality of molding layers are patterned to form a preliminary storage node hole that exposes a portion of the semiconductor substrate. The patterned molding layers are isotropically etched using the etchant, thereby forming a storage node hole. Therefore, the storage node hole has a stepped sidewall profile. A conformal conductive layer is then formed on the substrate and the conductive layer is planarized until a top surface of the molding layers is exposed.

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Seoul, South Korea

Si-Youn Kim