Micron Technology Incorporated

Lodestar Licensing Group LLC

Si-Woo Lee

Haitao Liu

Sangmin Hwang

John A Smythe

Scott E Sills

Kamal M Karda

Gurtej S Sandhu

Deepak Chandra Pandey

Armin Saeedi Vahdat

Byung Yoon Kim

Sanh D Tang

Srinivas Pulugurtha

Kyuseok Lee

Chandra V Mouli

Fatma Arzum Simsek-Ege

Tae Hyoung Kim

Terrence B McDaniel

Guangjun Yang

Kevin J Torek

Scott L Light

Brent D Gilgen

Alex J Schrinsky

Rajesh N Gupta

Lars P Heineck

Yi Fang Lee

Jaydip Guha

Litao Yang

Vinay Nair

Russell A Benson

Sourabh Dhir

Song Guo

Sheng-Wei Yang

Mark A Zaleski

Silvia Borsari

Mohd Kamran Akhtar

Yunfei Gao

Luca Fumagalli

Zhiqiang Xie

Devesh Dadhich Shreeram

Fredrick David Fishburn

Sheng Wei Yang

Yuichi Yokoyama

Kangle Li

Ashwin Panday

An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

Array of vertical transistors and method used in forming an array of vertical transistors

Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

Epitaxial single crystalline silicon growth for a horizontal access device

Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complementary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

Single crystalline silicon stack formation and bonding to a cmos wafer

An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

Channel conduction in semiconductor devices

A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.

Microelectronic devices and memory devices

A variety of applications can include apparatus having a recessed channel FinFET. The recessed channel FinFET can include one or more fin structures between the source region and the drain region, where the one or more fin structures are recessed from a top level of the source region and from a top level of the drain region. The recessed channel FinFET can include a gate recessed from the top level of a source region and a drain region, where the gate can be separated from tip regions of the fin structures by a gate dielectric defining a channel between the source region and the drain region. Recessed channel FinFETs can be structured in a periphery to an array of a memory device and can be fabricated in a process merged with forming access lines to the array.

Recessed channel fin integration

Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.

Conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices

Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complimentary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

Single crystalline silicon stack formation and bonding to a CMOS wafer

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.

Bottom electrode contact for a vertical three-dimensional memory

A microelectronic device comprises semiconductive pillar structures each individually comprising a digit line contact region disposed laterally between two storage node contact regions. At least one semiconductive pillar structure of the semiconductive pillar structures comprises a first end portion comprising a first storage node contact region, a second end portion comprising a second storage node contact region, and a middle portion between the first end portion and the second end portion and comprising a digit line contact region, a longitudinal axis of the first end portion oriented at an angle with respect to a longitudinal axis of the middle portion. Related microelectronic devices, electronic systems, and methods are also described.

Microelectronic devices including semiconductive pillar structures, and related electronic systems

Systems, methods, and apparatus including multi-direction conductive lines and staircase contacts for semiconductor devices. One memory device includes an array of vertically stacked memory cells, the array including: a vertical stack of horizontally oriented conductive lines, each conductive line comprising: a first portion extending in a first horizontal direction; and a second portion extending in a second horizontal direction at an angle to the first horizontal direction.

Multi-direction conductive line and staircase contact for semiconductor devices

Systems, methods, and apparatuses are provided for self-aligned etch back for vertical three dimensional (3D) memory. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes removing portions of the semiconductor material to form first horizontal openings and depositing a fill in the first horizontal openings. The method can further include forming third vertical openings to expose third vertical sidewalls in the vertical stack and selectively removing the fill material to form a plurality of second horizontal openings in which to form horizontally oriented storage nodes.

Self-aligned etch back for vertical three dimensional (3D) memory

Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

Integrated memory with redistribution of capacitor connections, and methods of forming integrated memory

A microelectronic device comprises a semiconductive pillar structure comprising a central portion, a first end portion, and a second end portion on a side of the central portion opposite the first end portion, the first end portion oriented at an angle with respect to the central portion and extending substantially parallel to the second end portion, a digit line contact on the central portion of the semiconductive pillar structure, a first storage node contact on the first end portion, and a second storage node contact on the second end portion. Related microelectronic devices, electronic systems, and methods are also described.

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Boise, ID, United States of America

Si-Woo Lee