International Business Machines Corporation

Si T Win

Daniel Mark Dreps

Wiren Dale Becker

Glen Arthur Wiedemeier

Jose A Hejase

Jesus Montanez

Damon G Hodge

Method and apparatus for analyzing an electrical circuit design includes storing within a memory associated with a pin, a pin functional definition comprising a pin connection parameter, and comparing the pin connection parameter to a design parameter to determine a result pertaining to a pin connection. The memory may be internal or external to the pin.

Pin number definition based analytics

Embodiments of the present disclosure provide methods for using a compliance model to determine compatibility of a channel with a bus's chip I/O circuitry at its ends. The method includes identifying at least one design criteria and obtaining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. In certain embodiments, the boundary sets may be derived using a genetic algorithm. The method further includes verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

Frequency-domain high-speed bus signal integrity compliance model

Embodiments of the present disclosure provide methods for testing channel compliance. The method generally includes identifying at least one design criteria and determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. The boundary sets may be used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

Embodiments of the present disclosure provide apparatus for testing channel compliance. The apparatus generally performs operations that includes identifying at least one design criteria and determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. The boundary sets may be used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

Embodiments of the present disclosure provide apparatus for using a compliance model to determine compatibility of a channel with a bus's chip I/O circuitry at its ends. The apparatus includes at least one processor and a memory coupled to the at least one processor. The processor is configured to: identify at least one design criteria; obtain boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria; and verify whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

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Austin, TX, United States of America

Si T Win