Samsung Electro-mechanics Co., Ltd.

Si Joong Yang

Young Ki Lee

Young Hoon Kwak

Jong Man Kim

Young Ho Sohn

Seung Wook Park

Jin Su Kim

Tae Hyun Kim

Dong Hwan Kim

Bum Seok Suh

Kee Ju Um

Hyo Jin Lee

Jae Cheon Doh

Kwang Soo Kim

Tae Hoon Kim

Jae Hyun Lim

Do Jae Yoo

Job Ha

Yong Gil Namgung

Jingli Yuan

Joon Hyung Cho

Jing Li Yuan

Jong Cheol Hong

In Goo Kang

Byoung Heon Kim

Kyu Kwan Oh

An image sensor package includes a substrate, an image sensor mounted on the substrate, a bonding wire connecting the image sensor to the substrate, a reflector disposed on the image sensor, a sealing member sealing the bonding wire and a portion of the image sensor, and covering at least a portion of the reflector, the sealing member including a hole exposing an effective imaging plane of the image sensor, and a filter attached to the sealing member.

Image sensor package including reflector

Disclosed herein is an all-in-one power semiconductor module including a plurality of first semiconductor devices formed on a substrate; a housing molded and formed to include bridges formed across upper portions of the plurality of first semiconductor devices; and a plurality of lead members integrally formed with the housing and electrically connecting the plurality of first semiconductor devices and the substrate. According to the present invention, reliability can be improved by increasing bonding areas and bonding strength of semiconductor devices as well as processibilty can be enhanced and failure is reduced by adjusting a step difference with respect to an arrangement and height of the semiconductor devices. Further, a processing time resulting from an omission of a wire bonding process is reduced.

All-in-one power semiconductor module

Disclosed herein is a semiconductor module package, including: a first module including a first heat radiation substrate and one or more first semiconductor elements and having a first N terminal and a first P terminal formed at one end thereof; a second module including a second heat radiation substrate and one or more second semiconductor elements, having a second N terminal and a second P terminal formed at one end thereof, and disposed so as to face the first module; and a first output terminal formed by electrically connecting the first module to the second module.

Semiconductor module package

Semiconductor device

Power semiconductor module

Provided is a wafer level package fabrication method. The method includes providing a device substrate wafer including one or more devices on an upper surface thereof, and a bonding pad electrically connected to the device, providing a bonding seal surrounding the device along the bonding pad, bonding a cap substrate wafer to the device substrate wafer through the bonding seal, the cap substrate wafer having a via formed in a region corresponding to the bonding pad, forming an external terminal on the cap substrate wafer, the external terminal being electrically connected to the bonding pad, and cutting the cap substrate wafer and the device substrate wafer along a cutting line to individually separate a plurality of wafer level packages. The method is conducive to reducing product size for miniaturization, is capable of performing a bonding process without wafer deformation or damage, and increases freedom in wafer material selection.

Wafer level package fabrication method

Provided is a method for manufacturing a semiconductor package. In the method, a wafer for a cap substrate is provided. The wafer for the cap substrate includes a plurality of vias and via electrodes on a lower surface. A wafer for a device substrate is provided. The wafer for the device substrate includes a circuit unit and a connection electrode on an upper surface. The wafer for the cap substrate and the wafer for the device substrate are primarily bonded by a medium of a primary adhesive. A trench is formed to expose the upper surface of the wafer for the device substrate to an outside along an outer edge of the primary adhesive. A secondary bonding operation is performed by a medium of a secondary adhesive to electrically connect the via electrode and the connection electrode. The wafer for the device substrate is diced along a virtual cut line.

Method for manufacturing semiconductor package

Growing community of inventors

Suwon, South Korea

Si Joong Yang