Samsung Electronics Co., Ltd.

Si-Hong Kim

Kwang-il Park

Seung-Jun Bae

Young-Soo Sohn

Chul-woo Park

Jae-Youn Youn

Hyun-Joong Kim

Tae-Young Oh

Young-Hyun Jun

Jin-il Lee

Dae-Hyun Chung

Jin-gook Kim

Kwang-II Park

Yong-Gwon Jeong

Young-Hoon Sohn

Kwnag-Il Park

Yun-Seok Yang

A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

Memory device and memory system having the same

A memory device comprising: at least one bank of memory cells that receives a first clock for clocking commands and a second clock for clocking data, wherein the second clock is activated based on a first command and deactivated based on a second command. The memory device further including a clock activation circuit configured to generate an enable signal based on the first command and a disable signal based on the second command, and a clock generator configured to generate the second clock based on a reference clock upon receipt of the enable signal.

Memory controller with reduced power consumption, memory device, and memory system

A stacked semiconductor memory device according to the inventive concepts may include a plurality of memory chips stacked above a processor chip, a plurality of TSVs, and I/O buffers. The TSVs may pass through the memory chips and are connected to the processor chip. I/O buffers may be coupled between all or part of the memory chips and the TSVs and may be selectively activated on the basis of defective states of the TSVs.

Stacked semiconductor memory device, memory system including the same, and method of repairing defects of through silicon vias

A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.

Data output buffer and memory device

A temperature sensing circuit of a semiconductor device includes a code signal generator, a comparator, a reference clock generator and a final temperature code signal generator. The code signal generator is configured to output a first count signal having an increase rate that varies according to a change in temperature. The comparator is configured to receive the first count signal and a control signal, compare the first count signal with the control signal and output a comparison signal. The reference clock generator is configured to generate a reference clock having a uniform period regardless of the change in temperature during an activation period of the comparison signal. The final temperature code signal generator is configured to count pulses of the reference clock, generate a second count signal, modify the second count signal using an offset value, and output the modified second count signal as a final temperature code signal.

Temperature sensing circuit of semiconductor device

An AC-coupling phase interpolator and a DLL using the same are provided. The AC-coupling phase interpolator includes a coupling capacitor generating and outputting a coupling signal by AC-coupling to an interpolation signal obtained by phase-interpolating an input signal. Thereby, it is possible to correct duty of an input signal and adjust the level of an output signal.

AC-coupling phase interpolator and delay-locked loop using the same

A semiconductor device includes a plurality of pads, where an external reference resistor is connected to a first one of the pads, an impedance calibrating unit configured to generate an impedance calibration code corresponding to an impedance of the reference resistor and output the impedance calibration code to a code transmitting line during a normal operating mode, and an impedance matching unit configured to perform an impedance matching operation in response to the impedance calibration code during the normal operating mode. The impedance calibrating unit is configured to output a test code to the code transmitting line in response to a test signal during a test operating mode. The impedance matching unit is configured to serialize the test code to output the serialized test code to each of the other pads in response to the test signal during the test operating mode.

Growing community of inventors

Yongin-si, South Korea

Si-Hong Kim