Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Inc.

International Business Machines Corporation

Nanyang Technological University

Shyue Seng Tan

Eng Huat Toh

Elgin Kiok Quek

Xinshu Cai

Kiok Boone Elgin Quek

Desmond Jia Jun Loy

Lanxiang Wang

Elgin Kiok Boone Quek

Lee Wee Teo

Yuan Sun

Yongshun Sun

Bin Liu

Danny Pak-Chum Shum

Jae Gon Lee

Xuan Anh Tran

Chung Foong Tan

Chunshan Yin

Shailendra Mishra

Vibhor Jain

Juan Boon Tan

John Joseph Pekarik

Yung Fu Chong

Chung Woh Lai

Zhao Lun

Ping Zheng

Johnny Widodo

Ruchil Kumar Jain

Jeffrey Chee

Khee Yong Lim

Yong Meng Lee

Ying Keung Leung

Qizhi Liu

Judson Robert Holt

Ming Zhu

Kien Seen Daniel Chong

Pengfei Guo

Kenneth J Stein

Wei Chang

Chew Hoe Ang

Tu Pei Chen

Sriram Balasubramanian

Yanzhe Tang

Gang Chen

Robert J Gauthier, Jr

Purakh Raj Verma

Alex See

Henry K Utomo

Sanford Chu

Sunil Kumar Singh

Guowei Zhang

Fan Zhang

Wei Lu

Steven R Soss

Wei Ling Chang

James Yong Meng Lee

Jeoung Mo Koo

Soh Yun Siah

Tze Ho Simon Chan

Benfu Lin

Danny Shum

Kazutaka Yamane

Zheng Zou

Lawrence Selvaraj Susai

Samarth Agarwal

Jianxun Sun

Francis YongWee Poh

Luona Goh

Jeffrey Chor-Keung Lam

Jiacheng Lei

James Jerry Joseph

Eng-Huat Toh

Yinjie Ding

Meng Yew Seah

Kian Hui Goh

Cancan Wu

Zar Lwin Zin

Thanh Hoa Phung

Ming Tsang Tsai

George Mulfinger

Kian Ming Ng

Jingze Tian

Yan Zhe Tang

Chun Shan Yin

The disclosed subject matter relates generally to structures for use in memory devices. More particularly, the present disclosure relates to three terminal resistive random-access (ReRAM) memory structures having source, drain, and control electrodes. The present disclosure provides a memory structure including a source electrode having an upper surface, a drain electrode having an upper surface, a dielectric channel layer laterally between the first electrode and the second electrode, a hole generating layer on the dielectric channel layer, and a control electrode on the hole generating layer, the control electrode has an upper surface. The upper surface of the control electrode is substantially coplanar with the upper surface of the source electrode and the upper surface of the drain electrode.

Structures for three-terminal memory cells

The present disclosure relates to a structure which includes a semiconductor substrate, a recessed shallow trench isolation structure within the semiconductor substrate, and a gate structure provided at least partially over the recessed shallow isolation structure.

Wrap-around memory circuit

A ferroelectric transistor (FeFET) memory device includes a metal gate, a gate dielectric layer adjacent to the metal gate, a semiconductor channel layer adjacent to the gate dielectric layer, a metal drain electrode, and a metal source electrode recessed into the semiconductor channel layer. The metal gate may be oriented above or below the metal source and drain electrodes with respect to a semiconductor substrate.

Fe-FET structure with buried electrode

Structures for a junction field-effect transistor and methods of forming a structure for a junction field-effect transistor. The structure comprises a first gate on a top surface of a semiconductor substrate, a second gate beneath the top surface of the semiconductor substrate, and a channel region in the semiconductor substrate. The first gate is positioned between a source and a drain, and the channel region positioned between the first gate and the second gate.

Junction field-effect transistors

The disclosed subject matter relates generally to structures for use in memory devices. More particularly, the present disclosure relates to three terminal resistive random-access (ReRAM) memory structures having source, drain, and control electrodes. The present disclosure provides a memory structure including a source electrode, a drain electrode, a control electrode laterally between the source electrode and the drain electrode, a hole generating layer above the control electrode, a dielectric channel layer above the hole generating layer, the dielectric channel layer contacts the source electrode and the drain electrode, a first spacer layer on a first side of the control electrode, and a second spacer layer on a second side of the control electrode. The first spacer layer and the second spacer layer isolate the source electrode and the drain electrode from the control electrode and the hole generating layer.

Structures for a non-volatile memory and methods of forming such structures. A gate electrode and a gate dielectric layer are formed over an active region with the gate dielectric layer between the gate electrode and the active region. A first doped region is formed in the active region, a second doped region is formed in the active region, and a source line is coupled to the second doped region. The first doped region is positioned in the active region at least in part beneath the gate dielectric layer, and the second doped region is positioned in the active region adjacent to the first doped region. The first doped region has a first conductivity type, and the second doped region has a second conductivity type opposite to the first conductivity type.

Non-volatile memory elements with one-time or multiple-time programmability

The disclosed subject matter relates generally to structures, memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having a spacer element on a side of the electrode. The present disclosure provides a memory device including a first electrode having a side, the side has upper and lower portions, a spacer element on the lower portion of the side of the first electrode, a resistive layer on the upper portion of the side of the first electrode, and a second electrode laterally adjacent to the side of the first electrode. The second electrode has a top surface, in which the top surface has a concave profile.

Memory devices and methods of making the same

A structure including a semiconductor layer having a body region of a first conductivity type and a first electrode including a doped region of a second conductivity type in the semiconductor layer is provided. The doped region is adjacent to the body region. The doped region includes a first portion and a second portion extending laterally from the first portion. The first portion has a first width and the second portion has a second width. The first width is greater than the second width. A ferroelectric layer is arranged on the semiconductor layer over the body region. A second electrode is arranged on the ferroelectric layer. The first portion and the second portion of the doped region partially underlap the second electrode.

Memory structures and methods of forming the same

A memory device and method of making the same is provided. The memory device includes a first electrode, an oxygen scavenging layer on the first electrode, a hard mask on the oxygen scavenging layer, and a second electrode on the hard mask. A switching layer is arranged on a portion of the oxygen scavenging layer, and the switching layer is conformal to a side surface of the hard mask.

Non-volatile memory device with filament confinement

The disclosed subject matter relates generally to structures, memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having two resistive layers and a conductive layer arranged between two electrodes. The present disclosure provides a memory device including a first electrode above an interlayer dielectric region, a second electrode above the interlayer dielectric region, the second electrode is laterally adjacent to the first electrode, a conductive layer between the first electrode and the second electrode, in which the conductive layer is electrically isolated, a first resistive layer between the first electrode and the conductive layer, and a second resistive layer between the second electrode and the conductive layer.

Lateral multi-bit memory devices and methods of making the same

Structures for an electronic fuse and methods of forming an electronic fuse. The structure includes a first terminal, a second terminal, and a fuse link extending from the first terminal to the second terminal. The structure further includes a silicide layer having a first portion included in the fuse link and a second portion included in the first terminal and the second terminal. The first portion of the silicide layer has a first thickness, the second portion of the silicide layer has a second thickness, and the first thickness is less than the second thickness.

Electronic fuses with a silicide layer having multiple thicknesses

The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted 'T' shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.

Transistor with wrap-around extrinsic base

The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region; an emitter region above the intrinsic base region; a collector region under the intrinsic base region; and an extrinsic base region comprising metal material, and which surrounds the intrinsic base region and the emitter region.

Bipolar transistors

The embodiments herein relate to semiconductor memory devices and methods of forming the same. A semiconductor memory device is provided. The semiconductor memory device includes a memory cell having a first electrode, a second electrode, a switching layer, and a via structure. The second electrode is adjacent to a side of the first electrode and the switching layer overlays uppermost surfaces of the first and second electrodes. The via structure is over the uppermost surface of the second electrode.

Semiconductor memory devices

A structure includes a photodetector including alternating p-type semiconductor layers and n-type semiconductor layers in contact with each other in a stack. Each semiconductor layer includes an extension extending beyond an end of an adjacent semiconductor layer of the alternating p-type semiconductor layers and n-type semiconductor layers. The extensions provide an area for operative coupling to a contact. The extensions can be arranged in a cascading, staircase arrangement, or may extend from n-type semiconductor layers on one side of the stack and from p-type semiconductor layers on another side of the stack. The photodetector can be on a substrate in a first region, and a complementary metal-oxide semiconductor (CMOS) device may be on the substrate on a second region separated from the first region by a trench isolation. The photodetector is capable of detecting and converting near-infrared (NIR) light, e.g., having wavelengths of greater than 0.75 micrometers.

Multi-semiconductor layer photodetector and related method

Growing community of inventors

Singapore, Singapore

Shyue Seng Tan