Powerchip Semiconductor Manufacturing Corporation

Powerchip Technology Corporation

Shyng-Yeuan Che

Shih-Ping Lee

Po-Yi Wu

Hsiao-Pei Lin

Kuo-Fang Huang

Bo-An Tsai

Wen-Yi Wong

Chi-Ching Liao

Hung-Tai Lai

S-i Chan

Chung-Ming Kuo

Hung-Yao Huang

Ching-Hsiu Wu

Hsin-Lan Hsueh

Chun-Chi Chou

The present disclosure provides a wafer chuck including a substrate and a heating/cooling wafer. The substrate includes a first surface facing a wafer to be carried and a second surface opposite to the first surface. The heating/cooling wafer is disposed on the first surface of the substrate and includes a plurality of heating/cooling units arranged in an array. In a direction perpendicular to the first surface, the positions of the heating/cooling units and the positions of a plurality of dies included in the wafer to be carried are corresponded with each other, and the heating/cooling units can heat or cool the corresponding dies individually.

Wafer chuck

A manufacturing method of an interconnect structure including the following is provided. A substrate is provided. Sacrificial layers are formed on the substrate. A dielectric layer is formed between two adjacent sacrificial layers. There is an air gap in the dielectric layer. The sacrificial layers are removed to form first openings. A conductive layer is formed in the first opening.

Manufacturing method of interconnect structure

Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.

Memory structure

Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.

A semiconductor structure and an integrated circuit are provided. The semiconductor structure includes first well regions and a second well region in a semiconductor substrate; first transistors within the first wells; second transistors within the second well; and bit lines. The first wells are separately arranged along a first direction and a second direction. The second well continuously spreads between the first wells. Each first transistor and one of the second transistors are adjacent and connected to each other via a common source or common drain. The common drain or common source is electrically connected to a storage capacitor, and the electrically connected first and second transistors as well as the storage capacitor form a memory cell. The bit lines respectively extend between adjacent rows of the first wells. Adjacent memory cells arranged along the second direction are electrically connected to the same bit line.

Semiconductor structure and integrated circuit

A memory structure including a SOI substrate, a first transistor, a second transistor, an isolation structure and a capacitor is provided. The SOI substrate includes a silicon base, a dielectric layer and a silicon layer. The first transistor and the second transistor are disposed on the silicon layer. The isolation structure is disposed in the silicon layer between the first transistor and the second transistor. The capacitor is disposed between the first transistor and the second transistor. The capacitor includes a body portion, a first extension portion, a second extension portion and a third extension portion. The first extension portion extends from the body portion to a source/drain region of the first transistor. The second extension portion extends from the body portion to a source/drain region of the second transistor. The third extension portion extends from the body portion, penetrates through the isolation structure and extends into the dielectric layer.

Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion and a dummy portion. The circuit portion is electrically connected to the first and second transistors. The dummy portion is located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.

Memory structure and manufacturing method thereof

A method for fabricating a multi-layer, crown-shaped MIM capacitor is provided. A base having therein a conductive region within a capacitor-forming region is formed. An IMD layer is deposited on the base to cover the capacitor-forming region. A capacitor trench is formed within the capacitor-forming region. The capacitor trench penetrates through the IMD layer, thereby exposing a portion of the conductive region. A concentric capacitor lower electrode structure is formed within the capacitor trench. The concentric capacitor lower electrode structure includes a first electrode and a second electrode surrounded by the first electrode. The first electrode is in direct contact with the conductive region. A conductive supporting pedestal is formed within the capacitor trench for fixing and electrically connecting bottom portions of the first and second electrodes. A capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal is formed.

Method for manufacturing multilayer crown-shaped MIM capacitor

A multi-layer, crown-shaped MIM capacitor includes a base having therein conductive region, an inter-metal dielectric (IMD) layer on the base, a capacitor trench penetrating through the IMD layer and exposing the conductive region, a capacitor lower electrode structure including a first electrode and a second electrode surrounded by the first electrode, a conductive supporting pedestal within the capacitor trench for fixing and electrically connecting the bottom portions of the first and second electrodes, a capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal, and a capacitor upper electrode on the capacitor dielectric layer.

Multilayer crown-shaped MIM capacitor and manufacturing method thereof

Provided is a capacitor structure including a substrate, a dielectric layer, a first conductive layer, and a cup-shaped capacitor. The dielectric layer is located on the substrate. The first conductive layer is located in the dielectric layer. The cup-shaped capacitor penetrates through the first conductive layer and is located in the dielectric layer. The cup-shaped capacitor includes a bottom electrode, a capacitor dielectric layer, and a top electrode. Two sidewalls of the bottom electrode are electrically connected to the first conductive layer. The capacitor dielectric layer covers a surface of the bottom electrode. The top electrode covers a surface of the capacitor dielectric layer. The capacitor dielectric layer is located between the top electrode and the bottom electrode. A top surface of the bottom electrode is lower than a top surface of the top electrode. Also the invention provides a method of manufacturing the capacitor structure.

Capacitor structure and method of manufacturing the same

An image sensor device includes a substrate having an active array region and a peripheral circuit region, a plurality of light-sensing elements disposed within the active array region, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer. A recess region is provided in the second dielectric layer to reveal a top surface of the first dielectric layer within the active array region. An angle between a sidewall of the second dielectric layer that defines the perimeter of the recess region and the top surface of the first dielectric layer is less than 90 degrees.

Growing community of inventors

Hsinchu County, Taiwan

Shyng-Yeuan Che