Taiwan Semiconductor Manufacturing Comp. Ltd.

Shyh-Wei Wang

Yen-Ming Chen

Jui-Yao Lai

Chun-Yi Lee

Da-Wen Lin

Jiann-Tyng Tzeng

Carlos H Diaz

Ta-Pen Guo

Ka-Hing Fung

Ying-Keung Leung

Chung-Cheng Wu

David Barry Scott

Min Cao

Chun-Fai Cheng

Hsiang-Jen Tseng

Shyue-Shyh Lin

Li-Ping Huang

Sheng-Jier Yang

Jin-Mu Yin

Ali Keshavarzi

Chin-Te Su

Ka Hing Fung

Ying-Shiou Lin

Jyh-Huei Chen

Chung-Yu Chiang

Chun-Hung Ko

A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.

Semiconductor device and method for forming same

The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes receiving a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10&#xb0; to about 25&#xb0; from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed.

Strained asymmetric source/drain

A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region.

Integrated circuits and manufacturing methods thereof

Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer.

Methods and apparatus for bipolar junction transistors and resistors

The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes providing a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10&#xb0; to about 25&#xb0; from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed.

Methods of fabricating a semiconductor device including a metal gate transistor and a resistor are provided. A method includes providing a substrate including a transistor device region and an isolation region, forming a dummy gate over the transistor device region and a resistor over the isolation region, and implanting the resistor with a dopant. The method further includes wet etching the dummy gate to remove the dummy gate, and then forming a metal gate over the transistor device region to replace the dummy gate.

Integrated circuit resistor fabrication with dummy gate removal

A method for manufacturing the integrated circuit device comprises providing a substrate having a first region, a second region, and a third region. A first dielectric layer is formed in the first region of the substrate. A second dielectric layer is formed in the second region and the third region. A sacrificial layer is formed over the first dielectric layer and the second dielectric layer. The sacrificial layer, the first dielectric layer, and the second dielectric layer are patterned to form a first gate stack, a second gate stack, and a third gate stack. An interlayer dielectric (ILD) layer is formed in between the first gate stack, the second gate stack, and the third gate stack. The second gate stack is removed to form an opening adjacent to the ILD layer and a third dielectric layer is formed in the opening.

Fabrication methods of integrated semiconductor structure

A method for manufacturing the integrated circuit device comprises providing a substrate having a first region, a second region, and a third region. A first gate stack, a second gate stack, and a third gate stack are formed over the substrate in the first region, the second region, and the third region, respectively. The first gate stack, the second gate stack, and the third gate stack comprise a sacrificial layer over a first dielectric layer. The first gate stack and the second gate stack are removed and a second dielectric layer is formed in the first region and the second region. The portion of second dielectric layer in the first region is transformed into a third dielectric layer by a treatment.

An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance.

An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. An exemplary method includes providing a substrate; forming a first gate over the substrate for a first device having a first threshold voltage characteristic, the first gate including a first material having a first-type work function; forming a second gate over the substrate for a second device having a second threshold voltage characteristic that is greater than the first threshold voltage characteristic, the second gate including a second material having a second-type work function that is opposite the first-type work function; and configuring the first device and the second device as a same channel type device.

Multi-threshold voltage device and method of making same

A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.

Growing community of inventors

Hsinchu, Taiwan

Shyh-Wei Wang