Industrial Technology Research Institute

Nan Ya Technology Corporation

Higgs Opl. Capital LLC

Winbond Electronics Corporation

Promos Technologies, Inc

Powerchip Semiconductor Corporation

Shyh-Shyuan Sheu

Pei-Chia Chiang

Wen-Pin Lin

Lieh-Chiu Lin

Chih-Sheng Lin

Chih-He Lin

Sih-Han Li

Meng-Fan Chang

Wei-Jen Chang

Pi-Feng Chiu

Kuan-Wei Chen

Jan-Ruei Lin

Shih-Chieh Chang

Ku-Feng Lin

Pei-Ling Tseng

Keng-Li Su

Fu-Cheng Tsai

Erh-Hao Chen

Chia-Chen Kuo

Ya-Wen Yang

Ra-Min Tain

Chen-Pang Kung

Ming-Ji Dai

Shih-Hsien Wu

Tuo-Hung Hou

Heng-Yuan Lee

Jeng-Hua Wei

Jian-Wei Su

Chih-Ping Cheng

Tay-Jyi Lin

Ming-Hung Wu

Zhe-Hui Lin

Min-Chuan Wang

Hsin-Chi Lai

Yi-Ching Kuo

Ching-Hao Chuang

Jan-Ruel Lin

An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

Apparatus and method for neural network computation

A data feature augmentation system and method for a low-precision neural network are provided. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample-and-hold circuit and a subtractor. The first sample-and-hold circuit is used for receiving an input signal and obtaining a first signal according to the input signal. The first signal is related to a first leakage rate of the first sample-and-hold circuit and the first signal is the signal generated by delaying the input signal by one time unit. The subtractor is used for performing subtraction on the input signal and the first signal to obtain a time difference signal. The input signal and the time difference signal are inputted to the low-precision neural network.

Data feature augmentation system and method for low-precision neural network

A neuron circuit and an artificial neural network chip are provided. The neuron circuit includes a memristor and an integrator. The memristor generates a pulse train having an oscillation frequency when an applied voltage exceeds a predetermined threshold. The integrator is connected in parallel to the memristor for receiving and accumulating input pulses transmitted by a previous layer network at different times, and driving the memristor to transmit the pulse train to a next layer network when a voltage of the accumulated input pulses exceeds the predetermined threshold.

Neuron circuit and artificial neural network chip

A readout circuit for a sensor and a readout method thereof are provided. The readout circuit includes a reference circuit, a compensated circuit, and a signal processing circuit. The reference circuit provides a direct current (DC) signal. The compensated circuit is coupled to the reference circuit. The compensated circuit obtains an analog sensing signal of the sensor, obtains the DC signal from the reference circuit, and provides a compensated signal according to the analog sensing signal and the DC signal. The signal processing circuit is coupled to the compensated circuit. The signal processing circuit processes the compensated signal to convert the compensated signal into a digital sensing signal. The compensated circuit subtracts the DC signal from the analog sensing signal to provide the compensated signal.

Readout circuit for sensor and readout method thereof

A method of manufacturing a sensor device is provided. In the method, sensing electrodes are formed on a substrate, a sensing material layer is formed on the sensing electrodes. The sensing material layer is etched to form a first nanowire sensing region, a second nanowire sensing region and a third nanowire sensing region respectively between every two sensing electrodes of the sensing electrodes. A dielectric layer is formed to cover the first nanowire sensing region, the second nanowire sensing region and the third nanowire sensing region, and the first nanowire sensing region and the third nanowire sensing region are exposed.

Method of manufacturing sensor device

A sensor device and a method of manufacturing the same are provided. The sensor device includes a substrate, a plurality of sensing electrodes, a humidity nanowire sensor, a temperature nanowire sensor, and a gas nanowire sensor. The sensing electrodes are formed on the substrate, and the humidity, the temperature and the gas nanowire sensors are also on the substrate. The humidity nanowire sensor includes an exposed first nanowire sensing region, the temperature nanowire sensor includes a second nanowire sensing region, and the gas nanowire sensor includes a third nanowire sensing region.

Sensor device and method of manufacturing the same

A sensor interface circuit and sensor output adjusting method are provided. The sensor interface circuit includes a processor and a gain control circuit. The processor obtains information of a linear region of a sensor to set a configuration corresponding to the sensor. The gain control circuit is coupled to the processor, performs a return-to-zero operation for a maximum electronic value and a minimum electronic value corresponding to the linear region and performs a full-scale operation for a slope of the linear region according to the maximum input range of an analog-to-digital converter which is a subsequent-stage circuit of the sensor interface circuit.

Sensor interface circuit and sensor output adjusting method

A variable-resistance memory and a writing method thereof are provided. The variable-resistance memory includes a variable-resistance memory cell, a voltage-signal-generation circuit, a switch circuit, a detection circuit, and a controller. The variable-resistance memory cell includes a variable-resistance component and a transistor. The voltage-signal-generation circuit is coupled to the control terminal of the transistor. The switch circuit is coupled to the variable-resistance component and transistor. The detection circuit is coupled to a voltage source and the switch circuit. The controller is coupled to the voltage-signal-generation circuit, switch circuit, and detection circuit. When the controller performs a writing operation on the variable-resistance memory cell, the voltage-signal-generation circuit provides a voltage signal to the transistor, and the detection circuit continuously detects whether the variable-resistance component performs a resistance conversion. If the resistance conversion occurs, then the controller stops the writing operation.

Variable-resistance memory and writing method thereof

A resistive memory system, a driver circuit thereof and a method for setting resistances thereof are provided. The resistive memory system includes a memory array, a row selection circuit, a first control circuit and a second control circuit. The memory array has a plurality of resistive memory cells. The row selection circuit is used for activating the resistive memory cells. The first control circuit and the second control circuit are coupled to the resistive memory cells. When each of resistive memory cells is set, the first control circuit and the second control circuit respectively provide a set voltage and a ground voltage to the each of resistive memory cells to form a set current, and the set current is clamped by at least one of the first control circuit and the second control circuit.

Resistive memory system, driver circuit thereof and method for setting resistance thereof

A resistive random-access memory device includes a memory array, a read circuit, a write-back logic circuit and a write-back circuit. The read circuit reads the data stored in a selected memory cell and accordingly generates a first control signal. The write-back logic circuit generates a write-back control signal according to the first control signal and a second control signal. The write-back circuit performs a write-back operation on the selected memory cell according to the write-back control signal and a write-back voltage, so as to change a resistance state of the selected memory cell from a low resistance state to a high resistance state, and generates the second control signal according to the resistance state of the selected memory cell.

Resistive random-access memory devices

TSV repair circuit of a semiconductor device includes a first chip, a second chip, at least two TSV, at least two data path circuits and an output logic circuit. Each data path circuit comprises an input driving circuit, a TSV detection circuit, a memory device, a protection circuit and a power control circuit. The TSV detection circuit detects a TSV status, the memory device keeps the TSV status, the protection circuit determines whether to pull a first end of the TSV to a ground voltage according to the TSV status, and the power control circuit prevents a leakage current of a power voltage from flowing through a substrate.

Through silicon via repair circuit of semiconductor device

A memory storage circuit includes a volatile memory portion, a control portion, and a non-volatile memory portion. The volatile memory portion includes a first node and a second node to store a pair of complementary logic data. The control portion includes a first transistor and a second transistor. Gate electrodes of the first and second transistors are coupled to receive a store signal, and first electrodes of the first and second transistors are coupled to receive a control signal. The non-volatile memory portion includes a first resistive memory element and a second resistive memory element to store the pair of complementary logic data. The first resistive memory element is coupled between a second electrode of the first transistor and the first node, and the second resistive memory element is coupled between a second electrode of the second transistor and the second node.

Memory storage circuit and method of driving memory storage circuit

A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit.

Configurable logic block and operation method thereof

An embodiment of a writing system for a phase change memory based on a present application is disclosed. The writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit. The first writing circuit executes a writing procedure, receives and writes a first data to the first PCM cell. The verifying circuit executes a verifying procedure and the circuit further comprises a processing unit and a second writing circuit. The processing unit reads and compares the data stored in the second PCM cell with a second data. The second writing circuit writes the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched.

Writing system and method for phase change memory

A verification circuit for a phase change memory array is provided. A sensing unit senses a sensing voltage from a memory cell of the phase change memory array according to an enable signal. A comparator generates a comparing signal according to the sensing voltage and a reference voltage, so as to indicate whether the memory cell is in a reset state. A control unit generates a control signal according to the enable signal. An operating unit generates a first signal according to the control signal, so as to indicate whether the comparator is active. An adjustment unit provides a writing current to the cell, and increases the writing current according to the control signal until the comparing signal indicates that the memory cell is in a reset state.

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Taichung, Taiwan

Shyh-Shyuan Sheu