Taiwan Semiconductor Manufacturing Comp. Ltd.

Shyh-Jye Wang

Chi-Chiang Wu

Hsing-Chien Huang

Wen-Hsiang Huang

A programmable non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The present invention also includes a first logic gate, whose first input terminal is coupled to receive an inverted signal of the primary clock signal. Further, the first input terminal of a second logic gate is coupled to receive the primary clock signal. A first programmable delay means, connected between an output of the first logic gate and the second input terminal of the second logic gate, is used to delay an output signal from the first logic gate a predetermined amount of time according to the selection signal. Moreover, a second programmable delay means, connected between an output of the second logic gate and the second input terminal of the first logic gate, is used to delay an output signal from the second logic gate a predetermined amount of time according to the selection signal. The programmable non-overlap clock generator therefore generates a first clock signal from the output of the first logic gate, and generates a second clock signal from the output of the second logic gate, wherein the first clock signal and the second clock signal are not logically active at the same time.

Programmable non-overlap clock generator

A structure and method for forming multiplication of a b-bit multiplicand X and a b-bit multiplier Y to generate a product P is disclosed. The present invention includes cells C.sub.mn configured in a b.times.b array, and pieces of means for generating partial product X.sub.mn, wherein outputs of the partial product generating means are connected to first inputs of the cells respectively. The second inputs of the cells C.sub.mn, where m=0, 1, 2, . . . , b-2, and n=1, 2, . . . , b-1, are connected to first outputs of the cells C.sub.m+1, n-1 respectively, and the second inputs of the cells C.sub.b-1, n, where n=1, 2, . . . , b-1, are connected to second outputs of the cells C.sub.n-1, b-1 respectively. Further, the third inputs of the cells C.sub.mn, where m=0, 1, 2, . . . , b-1, and n=2, 3, . . . , b-1, are connected to the second outputs of the cells C.sub.m, n-1. Therefore, a portion of the product P.sub.f, where f=0, 1, . . . , b-1, comes from the first outputs of the cells C.sub.0, f, another portion of the product P.sub.g, where g=b, b+1, . . . , 2b-1, comes from the first outputs of the cells C.sub.g-3, b-1, and a most significant bit P.sub.2b-1 of the product comes from the second output of the cell C.sub.b-1,b-1.

Structure and method of array multiplication

A power-on reset circuit (28) is disclosed. The circuit includes a first stage circuit (30) and a second stage circuit (32). The first stage circuit includes an input terminal coupled to receive an input signal, a latch for detecting a power-on condition, and an output terminal for providing a first stage circuit output signal. The first stage circuit output signal remains in a first state after detection of the power-on condition. The second stage circuit includes an input terminal coupled to receive the first stage circuit output signal, a latch for detecting the power-on condition, and an output terminal for providing a second stage circuit output signal. The second stage circuit output signal remains in the first state after detection of the power-on condition. The first stage circuit output signal changes state from the first state to a second state when the input signal changes state from the second state to the first state, and the second stage circuit output signal changes state from the first state to the second state only the first time that the first stage circuit output signal changes state from the first state to the second state.

Power-on reset circuit without an RC Network

A self-setup non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The present invention also includes a first logic gate having a first input terminal coupled to receive an inverted signal of the primary clock signal. Further, a second logic gate is provided, having a first input terminal coupled to receive the primary clock signal. A first programmable delay portion is used to delay an output signal from the first logic gate an amount of time according to the selection signal, and a second programmable delay portion is used to delay an output signal from the second logic gate a predetermined amount of time according to the selection signal. Therefore, a first clock signal is generated from the output of the first logic gate, and a second clock signal is generated from the output of the second logic gate. Particularly, the present invention includes a test circuit to determine whether a non-overlap space between the first clock signal and the second clock signal conforms to a predetermined value. Finally, a selector is used to generate the at least one selection signal in response to at least one output of the test circuit such that a smallest value out of all possible non-overlap spaces is chosen.

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Hsinchu, Taiwan

Shyh-Jye Wang