Advanced Semiconductor Engineering, Inc.

Shyh-Ing Wu

Shih-Kuang Chen

Chun-Chi Lee

Kun-Ching Chen

Tsung-Hua Wu

Yung-I Yeh

Chueh-An Hsieh

Li-Cheng Tai

Kuan-Neng Liao

Wu-Chang Wang

Tsung-Chieh Ho

Chun-Hung Lin

Su Tao

Ho-Ming Tong

Jen-Kuang Fang

Yung-Chi Lee

Yu-Chen Chou

Chun-Che Lee

Shin-Hua Chao

Yao-Hsin Feng

Ching-Fu Horng

Tao-Yu Chen

Shin Hua Chao

Jiunn Chen

Jui-I Yu

Jaw-Shiun Hsieh

Cheng-Hsueh Su

Gin-Nan Yeh

Hsing-Fu Lu

Chin-Pei Tien

Yao Shin Fang

Chun-Hsiung Huang

A method for forming a passivation layer is disclosed. In the method, a substrate containing a top surface and a bottom surface opposite to the top surface is first provided, wherein a plurality of conductive pads are disposed on the top surface thereof. Thereafter, a first passivation layer is formed on the top surface of the substrate, wherein the first passivation layer has a characteristic of photoresist. A first exposure/develop step is then performed to form a plurality of first openings in the first passivation layer, wherein the conductive pads are exposed through the first openings. Then, a second passivation layer is formed on the first passivation layer, wherein the second passivation layer has a characteristic of photoresist. A second exposure/develop step is then performed to form a plurality of second openings in the second passivation layer, wherein the conductive pads are exposed through the second openings.

Method for forming passivation layer

A bumping process and a structure thereof are provided. The bumping process includes the following steps. Firstly, a wafer having a number of pads is provided. Next, a UBM layer is formed on the pad. Then, a conductive first photo-resist layer is coated on the wafer to cover the UBM layer. Next, a second photo-resist layer is coated on the first photo-resist layer. Then, at least a portion of the second photo-resist layer is removed to form an opening above the UBM layer. The first photo-resist layer maintains electric connection with the UBM layer. Next, a solder layer is formed in the opening by electroplating process. Then, the first photo-resist layer and the second photo-resist layer are removed expect the portion of the first photo-resist layer under the solder layer.

Bumping process and structure thereof

A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.

Wafer structure with a multi-layer barrier in an UBM layer network device with power supply

An improved method of integrally attaching a heat sink to an IC package for enhancing the thermal conductivity of the package. A heat sink matrix, which is dividable into a plurality of individual heat sinks, is attached to an IC package matrix, which is comprised of a plurality of individual IC packages abutting each other in a matrix arrangement. The IC package matrix and the heat sink matrix attached thereto are then simultaneously cut by means of a machine tool into a plurality of individually formed IC packages each with a heat sink attached; thereby, thermal conductivity of a conventional IC package is enhanced.

Method of attaching a heat sink to an IC package

A solder paste for fabricating bumps includes a flux and metallic alloy powder. The metallic alloy powder includes a plurality of low eutectic metallic alloy granules, and the size of these metallic alloy granules is 20-60 &mgr;m and the average size of the metallic granules is 35 &mgr;m to 45 &mgr;m.

Solder paste for fabricating bump

A laser method for forming vias comprises: providing a heat sink; locally oxidizing a surface of the heat sink into a copper oxide film; bonding a substrate onto the heat sink at the copper oxide layer locations, wherein the substrate comprises at least a patterned trace layer and an insulating layer to which is bonded the heat sink, the insulating layer comprising a plurality of through holes that expose the portions of the copper oxide film; removing the copper oxide exposed through the through holes by laser beam; disposing a plurality of solder balls respectively in the through holes; and reflowing the solder balls to form a plurality of vias.

Laser method for forming vias

A method of making a ball grid array package comprises the steps of: (a) providing a film having an opening defined therein; (b) placing the film on a substrate; (c) attaching a semiconductor chip onto the substrate such that the semiconductor chip is positioned in the opening of the film; (d) electrically coupling the semiconductor chip to the substrate; (e) providing a molding die having a runner, a gate and a molding cavity defined therein, wherein the runner is connected to the molding cavity through the gate; (f) closing and clamping the molding die in a manner that the semiconductor chip is positioned in the molding cavity wherein the edges of the molding cavity fit entirely within the opening of the film and the edges of the runners and the gates are entirely positioned against the film; (g) transferring a hardenable molding compound into the molding cavity; (h) hardening the molding compound; (i) unclamping and opening the molding die; and (j) simultaneously removing the film and degating. The film in accordance with the present invention is characterized in that the adhesive force between the film and the molding compound is greater than the adhesive force between the film and the substrate. This makes the film tend to adhere to the excess molding compound; hence, the film will be removed along with the excess molding compound during the step (j) thereby automating the molding process.

Method of making ball grid array package

A packaged semi-conductor substrate includes a package encapsulant pouring area, a layout provided on the substrate, a layer of solder mask deposited on the layout, and a film provided on the solder mask. When the package encapsulant is pouted into the package encapsulant pouring area, the package encapsulant is isolated from the solder mask by the film. An adhering force between the film and the package encapsulant is greater than an adhering force between the film and the mask such that the film is degated along with the package encapsulant in the pouring channel during a degating procedure of the pouring channel after a pouring procedure of the package encapsulant. Thus, the film and the package encapsulant are not residual on the substrate.

Packaged semiconductor substrate

A semiconductor packaging device includes a printed circuit board substrate, a mold gate formed on a periphery of the printed circuit board substrate through which a package encapsulant is poured to enclose electric elements mounted on a side of the printed circuit board, and a layer of non-metallic material covered on the side of the printed circuit board substrate in the mold gate area. The package encapsulant, after hardened, is bonded with the layer of non-metallic material, and the bonded package encapsulant/the layer of non-metallic material is degatable from the mold gate.

Semiconductor packaging device

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Kaohsiung, Taiwan

Shyh-Ing Wu