Springsoft, Inc.

Springsoft Usa, Inc.

Shyh-Chang Lin

Po-Hung Lin

Yao-Wen Chang

Ho-Che Yu

Tian-Hau Tsai

Tung-Chieh Chen

Wei-Chung Chao

Chia-Huei Lee

Bang-Hwa Ho

Tai-Chen Chen

Feng-Yuan Chang

Yu-Sheng Lu

Shi-Hong Bai

A placement tool generates an optimal placement for a plurality of device modules within an analog integrated circuit (IC) subject to device matching, symmetry, and proximity constraints by first defining a multiple-level hierarchy of constraint groups, wherein each constraint group consists of elements that are subject to one of the placement constraints. Each element of each constraint group consists of either of one of the device modules or another one of the constraint groups residing at a lower level of the hierarchy. The tool then generates a hierarchical B*-tree representation of a trial placement for the IC including a separate node representing each constraint group of the hierarchy and a separate node for each of device module not included in any of the constraint groups. Each node representing a constraint group defines relative positions within the IC of each the device modules or lower level constraint groups forming the constraint group that are consistent with the placement constraint on the constraint group. The placement tool iteratively perturbs the hierarchical B*-tree to generate a sequence of trial placements for the IC design and then evaluates a cost function for each trial placement to select a best one of the trial placements as the optimal trial placement.

Hierarchical analog IC placement subject to symmetry, matching and proximity constraints

A computer-based placement and routing (P&R) tool stores a set of circuit patterns, each describing a separate device group by referencing each device of the device group and by indicating which device elements forming the referenced devices are interconnected by nets, a set of placement patterns, each providing a guide for placing IC device elements forming a device group described by a corresponding one of the circuit patterns and a set of routing styles to act as guides for routing nets between device elements placed in particular patterns. To produce a layout for an analog IC described by a netlist, the P&R tool identifies each set of devices in the IC forming a device group described by any of the circuit patterns. The P&R tool then generates a separate device group layout for each identified device group using the placement patterns as guides for placing device elements within the device group layout and using the routing styles as guides for routing nets interconnecting device elements within the device group layout. The P&R tool also generates a layout for each device not included in any identified device group. The tool then generates a layout for the IC incorporating each generated device and device group layout.

Analog and mixed signal IC layout system

A router organizes an IC area into an array of global routing cells (GRCs) and generates a congestion map providing a separate congestion factor for each GRC boundary. The router then iteratively partitions the IC area into progressively smaller tiles while selecting a route for each net passing between tiles when possible without altering any previously routed net. The router thereafter iteratively merges the tiles into progressively larger tiles while selecting a route for each previously unrouted net residing wholly within a single tile, altering routes of previously routed nets when necessary to accommodate the selected route. When selecting each route for any connection of a net, the router seeks to minimize a cost function of congestion factors of all GRC boundaries.

V-shaped multilevel full-chip gridless routing

To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions and all of the modules are allocated among those regions. The regions are then iteratively partitioning into smaller progressively smaller regions with modules previously allocated any partitioned region allocated among the regions into which it was partitioned, until each region of the floorplan has been allocated no more than a predetermined maximum number of modules. A separate floorplan is then generated for each region. Neighboring regions are then iteratively merged to create progressively larger regions, until only a single region remains, wherein upon merging any neighboring regions to form a larger merged region, the floorplans of the neighboring regions are merged and refined to create a floorplan for the merged region.

Multilevel IC floorplanner

A schematic diagram generator processes a netlist to generate a schematic diagram based on a set of placement rules, corresponding to a separate characteristic pattern of interconnected devices and specifying a constraint on relative placement within the schematic diagram of symbols representing devices forming the pattern. The generator identifies each set of devices in the netlist that exhibits any rule's interconnection pattern as a separate 'soft group', places a constraint consistent with the rule on relative positioning within the schematic diagram of symbols representing the soft group, resolves any constraint conflicts in accordance with a constraint resolution scheme, and then places all device symbols in the schematic diagram in a manner consistent accordance with the constraints.

Rule-based schematic diagram generator

A system for processing a netlist description of a circuit to generate a display of a schematic diagram including representations of cells and nets first determines positions of the cell instance representations within the schematic diagram and then displays the schematic diagram, including the cell instance representations but no representations of the nets. When a user requests a zoom in operation to display a smaller portion of the schematic diagram at a scale at which net representations can be viewed, the system determines routes for representations of nets that are to reside in that portion of the schematic diagram and then displays those net representations upon zooming in to that portion of the schematic diagram. When the user requests a pan operation to shift the display to another portion of the schematic diagram, the system determines routes for representations of nets that are to reside in that other portion of the schematic diagram and then displays those net representations upon panning to that other portion of the schematic diagram.

Schematic diagram generation and display system

A netlist of a schematic diagram is generated. The netlist indicates the connectivity of components through connection lines. A normal display mode is provided in which at least a portion of the components are presented on the display, and connection lines corresponding to the components are also displayed. A topology display mode is provided in which the components are presented on the display without the connection lines. The user can switch between the topology display mode and the normal display mode while editing the schematic diagram. Automatic pin assignment and routing of the connection lines is performed according to the netlist, and is based upon grouping similarly classified connection lines. An abstract display mode is provided that presents abstract lines for a selected component, with a single abstract line running between two connected components. The abstract display mode is combinable with the topology display mode. Finally, the automatic positioning of components according to predefined topology templates is provided.

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Hsinchu, Taiwan

Shyh-Chang Lin