Au Optronics Corporation

Ses Rfid Solutions Gmbh

Shyh-Bin Kuo

Chung-Hung Chen

Hsiang-Chi Cheng

Yi-Cheng Lai

Kuo-Hsiang Chen

Yu-Chih Wang

Sin-Jie Wang

Shih-Hsing Hung

Shih-Hsien Yang

Tai-Hsiang Huang

Martin Scattergood

A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.

Memory chip and operating method thereof

An ultrasonic detection device, including a substrate, sensing elements, a first test element, a first dummy element, at least one first common signal line, sensing signal lines, and at least one test signal line, is provided. The sensing elements, the first test element, and the first dummy element are located on the substrate. The first test element is located between the sensing elements and the first dummy element. Each of the sensing elements, the first test element, and the first dummy element includes an array of capacitive microelectromechanical ultrasonic transducers. The first common signal line is electrically connected to the sensing elements and the first test element. The sensing signal lines are electrically connected to the sensing elements. The test signal line is electrically connected to the first test element.

Ultrasonic detection device

An integrated circuit, a wireless communication card and a wiring structure of an identification mark are provided. The integrated circuit includes a power supply wiring, a ground wiring and at least one identification mark pattern. Each identification mark pattern has a first conductive wiring and a second conductive wiring that overlap each other, wherein the first conductive wiring is electrically connected to the power wiring, and the second conductive wiring is electrically connected to the ground wiring.

Integrated circuit, wireless communication card and wiring structure of identification mark

A chip is provided. The chip includes a flexible substrate, a plurality of thin-film transistors, a redistribution layer, a first power rail layer, and a second power rail layer. The plurality of thin-film transistors are disposed on the flexible substrate. The redistribution layer is disposed above the plurality of thin-film transistors. The first power rail layer is disposed above the redistribution layer. The first power rail layer provides a first voltage to the plurality of thin-film transistors. The second power rail layer is disposed above the first power rail layer. The second power rail layer provides a second voltage to the plurality of thin-film transistors, wherein the second power rail layer is disposed in a grid shape.

Chip having a flexible substrate

An antenna device includes a substrate, a chip, and an antenna. The chip is disposed on the substrate, and the chip has at least two pads. The antenna is disposed on the substrate, and the chip is disposed between the substrate and the antenna. The antenna has a first bonding line segment and a second bonding line segment electrically connected to the at least two pads respectively. The first bonding line segment is located at an outermost coil of the antenna, and is disposed across a short side direction of the chip in a manner of completely covering one of the at least two pads. The second bonding line segment is located at an innermost coil of the antenna, and is disposed across the short side direction of the chip in a manner of completely covering another of the at least two pads.

Antenna device and manufacturing method thereof

A chip is provided. The chip is provided with a circuit block. The circuit block includes a first transistor and a second transistor. The first transistor is divided into a plurality of first sub-transistors connected in parallel. The second transistor is divided into a plurality of second sub-transistors connected in parallel. The first sub-transistors and the second sub-transistors are disposed in a first row and a second row of the circuit block in a staggered manner. The first transistors disposed in the first row and the second row respectively receive a first input signal through different signal lines. The second transistors disposed in the first row and the second row respectively receive a second input signal through different signal lines.

Growing community of inventors

Hsinchu, Taiwan

Shyh-Bin Kuo