Tower Semiconductor Ltd.

Shye Shapira

Sharon Levin

Robert J Strain

Zachary K Lee

Ira Naot

Yossi Netzer

Ira Noat

A vertical DMOS device implements one or more deep silicon via (DSV) plugs, thereby significantly reducing the layout area and on-resistance (RDS) of the device. The DSV plugs extend through a semiconductor substrate to contact a conductively doped buried diffusion region, which forms the drain of the vertical DMOS device. Methods for fabricating the vertical DMOS device are compatible with conventional sub-micron VLSI processes, such that the vertical DMOS device can be readily fabricated on the same integrated circuit as CMOS devices and analog devices, such as lateral double-diffused MOS (LDMOS) devices.

Deep silicon via as a drain sinker in integrated vertical DMOS transistor

A Schottky diode exhibiting low series resistance is efficiently fabricated using a substantially standard CMOS process flow by forming the Schottky diode using substantially the same structures and processes that are used to form a field effect transistor (FET) of a CMOS IC device. Polycrystalline silicon, which is used to form the gate structure of the FET, is utilized to form an isolation structure between the Schottky barrier and backside structure of the Schottky diode. Silicide (e.g., cobalt silicide (CoSi)) structures, which are utilized to form source and drain metal-to-silicon contacts in the FET, are used to form the Schottky barrier and backside Ohmic contact of the Schottky diode. Heavily doped drain (HDD) diffusions and lightly doped drain (LDD) diffusions, which are used to form source and drain diffusions of the FET, are utilized to form a suitable contact diffusion under the backside contact silicide.

Gate defined Schottky diode

A Schottky diode is formed on an isolated well (e.g., a P-well formed in a buried N-well), and utilizes cobalt silicide (CoSi) structures respectively formed on heavily doped and lightly doped regions of the isolated well to provide the Schottky barrier and backside (ohmic) contact structures of the Schottky diode. The surrounding buried N-well is coupled to a bias voltage. The Schottky barrier and backside contact structures are separated by isolation structures formed using polycrystalline silicon, which is used to form the gate structure of CMOS FETs, in order to minimize forward resistance. Heavily doped drain (HDD) diffusions and lightly doped drain (LDD) diffusions, which are used to form source and drain diffusions of the FET, are utilized to form a suitable contact diffusion under the backside contact silicide.

Cobalt silicide schottky diode on isolated well

A low parasitic capacitance Schottky diode including a lightly doped polycrystalline silicon island that is formed on a shallow trench isolation (STI) pad such that the polycrystalline silicon island is entirely isolated from an underlying silicon substrate by the STI pad. The resulting structure reduces leakage and capacitive coupling to the substrate. Silicide contact structures are attached to lightly-doped and heavily-doped regions of the polycrystalline silicon island to form the Schottky junction and Ohmic contact, respectively, and are connected by metal structures to other components formed on the silicon substrate. The STI pad, polycrystalline silicon island, and silicide/metal contacts are formed using a standard CMOS process flow to minimize cost. A bolometer detector is provided by measuring current through the diode in reverse bias. An array of such detectors comprises an infrared or optical image sensor.

Growing community of inventors

Haifa, Israel

Shye Shapira