Texas Instruments-acer Incorporated

Powerchip Semiconductor Corporation

Other

Acer Semiconductor Manufacturing Corp.

Chip Integration Tech. Co., Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Vanguard International Semiconductor Corporation

Tsmc-acer Semiconductor Manufacturing Corporation

Acer Inc.

Texas Instruments Corporation

Texas Instruments - Acer Incorporate

Texas Instrumants - Acer Incorporated

Acer Semicondutor Manufacturing Inc.

Tsmc-acer Semiconductor Manufacturing Company

Shye-Lin Wu

Chung-Cheng Wu

Yih-Jau Chang

Li-Ping Huang

Hsi-Chuan Chen

Ming-Hong Kuo

Ling Chen

Bu-Chin Chung

Chung Cheng Wu

A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device includes a LOCOS structure grown on the bottom of the trenches by using nitride spacer on the sidewall of the trenches as a thermal oxidation mask. A polycrystalline silicon layer is then filled the first trenches. Under LOCOS structure, a p doped region is optionally formed to minimize the current leakage when the device undergoes a reverse biased. A Schottky barrier silicide layer formed by sputtering and annealing steps is formed on the upper surfaces of the epi-layer and the polycrystalline silicon layer. A top metal layer served as anode is then formed on the Schottky barrier silicide layer and extended to cover a portion of field oxide region of the termination trench. A metal layer served as a cathode electrode is then formed on the backside surface of the substrate opposite to the top metal layer.

High switching speed two mask schottky diode with high field breakdown

A method of forming silicon carbide Schottky diode is disclosed. The processes required two photo-masks only. The processes are as follows: firstly, an n+-silicon carbide substrate having an n&#x2212; silicon carbide drift layer is provided. Then a silicon layer is formed on the drift layer. An ion implant is carried out to dope the silicon layer. Afterward the doped silicon layer is patterned to define an active region. A thermal oxidation is then followed to form a thick oxide layer by oxidizing the silicon layer and form guard rings by using the doped silicon layer as a diffused source. The thin oxide layer on the drift layer is then removed by dilute HF dip or by BOE (buffer oxide etching) solution dip. Thereafter, a top metal layer is deposited and patterned to define as anode. After a backside layer removal, a metal layer served as cathode is formed.

Silicon carbide Schottky diode and method of making the same

A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structures, and definition of a conductive gate structure formed traversing the SOI fin type structures while interfacing the gate insulator layer. A doped insulator layer of a first conductivity type is formed on the exposed top surfaces of a first SOI fin type shape, while a second doped insulator layer of a second conductivity type is formed on the exposed top surfaces of the second SOI fin type shape. An anneal procedure results creation of a source/drain region of a first conductivity type in portions of the first SOI fin type shape underlying the first doped insulator layer, and creation of a source/drain region of a second conductivity type in portions of the second SOI fin type shape underlying the second doped insulator layer. Selective deposition of tungsten on exposed top surface of the source/drain regions is then employed to decrease source/drain resistance.

Method of forming an N channel and P channel finfet device on the same semiconductor substrate

A power Schottky rectifier device having a plurality of first trenches filled in with an un-doped polycrystalline silicon layer and each first trenches also has a p-region beneath the bottom of said first trenches to block out reverse current while a reverse biased is applied and to reduce minority carrier while forward biased is applied. Thus, the power Schottky rectifier device can provide first fast switch speed. The power Schottky rectifier device is formed with termination region at an outer portion of the substrate. The manufacture method is also provided.

Schottky barrier diode and method of making the same

A power Schottky rectifier device having pluralities of trenches are disclosed. The Schottky barrier rectifier device includes field oxide region having p-doped region formed thereunder to avoid premature of breakdown voltage and having a plurality of trenches formed in between field oxide regions to increase the anode area thereto increase forward current capacity or to shrinkage the planar area for driving the same current capacity. Furthermore, the trenches have rounded corners to alleviate current leakage and LOCOS region in the active region to relief stress during the bonding process. The processes for power Schottky barrier rectifier device including termination region formation need only three masks and thus can gain the benefits of cost down.

A power Schottky rectifier device and its fabrication method are disclosed. The method comprises the following steps: First, a semiconductor substrate having a relatively heavily doped n+ doped layer and a lightly doped is provided. A buried p region is then formed in the epi layer by ion implantation. Afterward, a first oxide layer and a nitride layer are then successively formed on the epi layer. The result structure is then patterned to form trenches. Subsequently, a thermal oxidation step is performed to recover etch damage. A wet etch is then performed to remove the thin oxide layer in the trench to expose the silicon in the sidewall. After that, a silicidation process is then performed to form silicide layer on the n-epi-layer in the trenches. After a removal of un-reacted metal layer, a top metal layer is then formed on the silicide layer and on the first oxide layer or nitride layer. The top metal layer on the termination region portion is then patterned to define anode. Finally, after backside layers formed on the rear surface of the substrate are removed, another cathode layer is formed on the rear surface.

High switching speed two mask Schottky diode with high field breakdown

A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device including a LOCOS structure and two p-type doping regions, which are positioned one above another therein to isolate cells so as to avoid premature of breakdown voltage. The Schottky rectifier device comprises: an n&#x2212; drift layer formed on an n+ substrate; a cathode metal layer formed on a surface of the n+ substrate opposite the n&#x2212; drift layer; a pair of field oxide regions and termination region formed into the n&#x2212; drift layer and each spaced from each other by the mesas, where the mesas have metal silicide layer formed thereon. A top metal layer formed on the field oxide regions and termination region and contact with the silicide layer. Under each of field oxide regions and termination region is a p doped and p&#x2212; doped region cascade which provide depleted regions enclosed the p&#x2212; doped regions to blocking the leakage current while a reverse bias voltage is exerted to the Schottky power rectifier diode.

Two mask shottky diode with locos structure

A Schottky diode structure and a method of making the same are disclosed. The method comprises following steps: firstly, a semiconductor substrate having a first conductive layer and an epi-layer doped with the same type impurities is provided. Then a first oxide layer is form on the epi layer. A patterning step to pattern first oxide layer and recess the epi layer (optional) is then followed to define guard rings. After stripping the photoresist pattern, a polycrystalline silicon layer formation is then followed. A boron and/or BF ion implant is then performed. Subsequently, a high temperature drive in process and oxidation process to oxidize the polycrystalline silicon layer and drive ions is then carried out. A second mask and etch steps are then performed to open the active regions. A metallization process is then done. A third mask and etch steps are then implemented to define anode. Finally, a backside metal layer is then formed and serves as a cathode.

Schottky diode with high field breakdown and low reverse leakage current

Method of forming an N channel and P channel FINFET device on the same semiconductor substrate

The ultra-short channel transistor in a semiconductor substrate includes a gate structure that is formed on the substrate. Side-wall spacers are formed on the side walls of the gate structure as an impurities-diffusive source. Source and drain regions are formed in the substrate. A metal silicide contact is formed on the top surface of the gate structure, and on the surface of the source and drain regions. Extended source and drain regions are formed beneath the side-wall spacers and connect next to the source and drain regions.

Ultra-short channel NMOSFETS with self-aligned silicide contact

A method of reducing the aspect ratio for dry etch processes used to form contact hole and storage node openings in composite insulator layers, to expose regions of CMOS devices used for embedded memory cell applications, has been developed. The method features formation of CMOS devices for an embedded memory cell in a recessed region of a semiconductor substrate, while peripheral, higher performing CMOS devices are formed on a non-recessed, SOI layer. Removal of a top portion of a first planarized insulator layer, only in the embedded memory cell region, allows reduction of the aspect ratio of a storage node opening formed in the bottom portion of the first planarized insulator layer. Formation of an overlying, second planarized insulator layer results in a composite insulator layer comprised of a thinned, second planarized insulator layer on the underlying first planarized insulator layer, in the peripheral CMOS device region. The thinned, second planarized insulator component of the composite insulator layer allows reduction of the aspect ratio for formation of a contact hole now defined in the composite insulator layer.

Method of fabricating three dimensional CMOSFET devices for an embedded DRAM application

A method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source/drain junctions is described. A gate structure having a gate insulating layer, a first conductive layer and a first dielectric layer is formed on a substrate. A thermal oxide layer is formed on the substrate and on sidewalls of the first conductive layer. The first dielectric layer is removed. Extended source and drain junctions are formed in the substrate under a region covered by the first thermal oxide layer. Sidewall spacers are formed on the sidewalls of the gate structure to protect the extended source and drain junctions therebeneath from being silicided. The second thermal oxide layer is removed to form recessed regions on a substrate surface. A first metal layer is formed on the substrate after the first dielectric layer is removed. Source/drain regions under the recessed regions are formed.

Method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source/drain junctions

A method of forming MOSFET with buried contacts and air-gap gate structure is disclosed. The method comprises following steps firstly, a gate is formed of pad oxide layer and a nitride layer sequentially on a silicon substrate, which has trench isolations. Then, a polysilicon layer and an oxide layer are deposited in order on all areas. Subsequently, an etched-back using the nitride layer a stopping layer is achieved. After that the nitride layer is removed thereby, forming a gate hollow region. After the pad oxide layer is removed, an oxynitride layer is regrown to be as the gate oxide. Thereafter, a silicon is deposited on all areas and refills in the gate hollow region. A planarization process is again performed using the oxide layer as an etch-stopping layer. Subsequently, the oxide layer is removed. S/D/G ion implanted into the polysilicon layer and the silicon layer. Then, the nitride spacers are removed to form dual recessed spaces. Another ion implantation is undertaken into first doped region and in a second doped region, which is in the bottom of the dual recessed spaces. A CVD oxide layer is then deposited on all areas and seals the dual recessed regions and forms the air-gaps. Finally an annealing process is carried out to form the shallow S/D, extended S/D junctions, and the buried contacts.

Method of forming MOSFET with buried contact and air-gap gate structure

The proposed method of the present invention forms MOSFETs with improved short channel effects and operating speeds over conventional devices. The method for fabricating MOSFETs includes the following steps. At first, isolation regions are formed on a semiconductor substrate and a gate insulating layer is formed on the substrate. A first conductive layer is then formed on the gate insulating layer and a first dielectric layer is formed on the first conductive layer. A removing process is performed to remove portions of the gate insulating layer, the first conductive layer and the first dielectric layer to define a gate structure. A layer formation step is carried out to form a thermal oxide layer on the substrate and on sidewalls the first conductive layer. Doped dielectric sidewall spacers are then formed on sidewalls of the gate structure. A removing step is carried out to remove portions of the thermal oxide layer uncovered by the doped dieletric sidewall spacers. Next, the first dielectric layer is removed and a doped silicon layer is selectively deposited on the first conductive layer and on exposed regions of substrate surface. A first metal layer is then formed on the substrate. A thermal process is carried out to drive in dopants in the doped dielectric sidewall spacers and the doped silicon layer, and to convert portions of the first metal layer into a metal silicide layer lying over the doped silicon layer. A removing step then removes unreacted portions of the first metal layer.

Method for fabricating ultra short channel PMOSFET with buried source/drain junctions and self-aligned silicide

The method for forming an isolation region in the present invention mainly includes the following steps. First, a pad layer is formed on a semiconductor substrate and an oxidation masking layer is formed on the pad layer. The oxidation masking layer, the pad layer, and the substrate are then patterned to form trenches in the substrate. The pad layer is removed laterally to form undercut structures under the oxidation masking layer. A doped layer is conformably formed on the oxidation masking layer, the undercut structures of the pad layer, and the substrate in the trenches. Next, a thermally oxidizing step is carried out to oxidize the doped layer to form an oxidized layer conformably on the oxidation masking layer, the undercut structures of the pad layer, and the substrate in the trenchs. A dielectric layer is formed over the substrate to fill up the trenches and cover over the pad layer and the oxidation masking layer. The dielectric layer is planarized downward to portions of the oxidation masking layer. Finally, the oxidation masking layer and the pad layer are removed.

Growing community of inventors

Hsinchu, Taiwan

Shye-Lin Wu