Micron Technology Incorporated

Nan Ya Technology Corporation

University of California

Intel Corporation

North Carolina State University

Shyam Surthi

Richard J Hill

Byeung Chul Kim

Jaydip Guha

Francois H Fabreguette

John David Hopkins

Suraj J Mathew

Lars P Heineck

Gurtej S Sandhu

Kamal M Karda

Matthew S Thorum

Purnima Narayanan

Hung-Ming Tsai

Jordan D Greenlee

Sheng-Wei Yang

Davide Resnati

Akira Goda

Jonathan S Lindsey

Paolo Tessariol

Kunal Shrotri

Ying-Cheng Chuang

David F Bocian

Zhiming Liu

Robert S Loewe

Amir A Yasseri

Qian Zhao

Qiliang Li

Sanh D Tang

Scott E Moore

John A Smythe

Gordon A Haller

Chris M Carlson

Vishwanath Bhat

Collin Howder

Anish A Khandekar

Shuang Meng

Niraj B Rana

Shane J Trapp

Litao Yang

Darwin Franseda Fan

Wolfgang Mueller

Veena Misra

Brian J Coppa

Gianpietro Carnevale

Michael E Koltonski

Veen Misra

Byeung Chui Kim

Sateesh Koka

Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions include conductive structures. The conductive structures have a first thickness. The proximal regions include insulative structures. The insulative structures have a second thickness at least about as large as the first thickness. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies

Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. Memory cells are along the conductive levels. The conductive levels have control gate regions which include a first vertical thickness, have routing regions which include a second vertical thickness that is less than the first vertical thickness, and have tapered transition regions between the first vertical thickness and the second vertical thickness. Charge-blocking material is adjacent to the control gate regions. Charge-storage material is adjacent to the charge-blocking material. Dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the vertical stack and is adjacent to the dielectric material. The memory cells include the control gate regions, and include regions of the charge-blocking material, the charge-storage material, the dielectric material and the channel material. Some embodiments include methods of forming integrated assemblies.

Methods of forming integrated assemblies with improved charge migration impedance

Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies

Some embodiments include an integrated assembly having a stack of alternating insulative levels and conductive levels. A pillar of channel material extends through the stack. The conductive levels have terminal regions adjacent the pillar. Charge-storage-material-segments are adjacent the conductive levels of the stack, and are between the channel material and the terminal regions. Tunneling material is between the charge-storage-material-segments and the channel material. Charge-blocking-material is between the charge-storage-material-segments and the terminal regions. Ribbons of dielectric material extend vertically across the insulative levels and are laterally inset relative to the terminal regions. The ribbons have first regions adjacent the conductive levels and have second regions between the first regions, with the second regions being laterally inset relative to the first regions. Some embodiments include methods of forming integrated assemblies.

Some embodiments include an integrated assembly having a stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions have first conductive structures, and the proximal regions have second conductive structures. Detectable interfaces are present where the first conductive structures join to the second conductive structures. Some embodiments include methods of forming integrated assemblies.

A microelectronic device comprises a stack structure, a staircase structure, an etch stop material, and insulative material. The stack structure comprises conductive structures, and air gaps vertically alternating with the conductive structures. The staircase structure is within the stack structure and has steps comprising edges of at least some of the conductive structures of the stack structure. The etch stop material continuously extends over the conductive structures and at least partially defines horizontal boundaries of the air gaps. The insulative material overlies the etch stop material. Additional microelectronic devices, memory devices, electronic systems, and methods are also disclosed.

Microelectronic devices including stack structures having air gaps, and related memory devices, electronic systems, and methods

Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions. High-k dielectric material is adjacent to the control gate regions and is configured as an arrangement of first vertically-extending linear segments which are vertically spaced from one another. Charge-blocking material is adjacent to the high-k dielectric material and is configured as an arrangement of second vertically-extending linear segments which are vertically spaced from one another. Charge-storage material is adjacent to the charge-blocking material and is configured as an arrangement of third vertically-extending linear segments which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies and methods of forming integrated assemblies.

Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include conductive structures. Channel material extends vertically through the stack. The conductive structures have proximal regions near the channel material, and have distal regions further from the channel material than the proximal regions. The insulative levels have first regions vertically between the proximal regions of neighboring conductive structures, and have second regions vertically between the distal regions of the neighboring conductive structures. Voids are within the insulative levels and extend across portions of the first and second regions. Some embodiments include methods for forming integrated assemblies.

An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

Electronic devices comprising adjoining oxide materials and related systems

Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. A channel material extends vertically along the stack. The channel material includes a semiconductor composition and has first segments alternating with second segments. The first segments are adjacent the wordline levels and the second segments are adjacent the insulative levels. The first segments have a first dopant distribution and the second segments have a second dopant distribution which is different from the first dopant distribution. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies having vertically-extending channel material with alternating regions of different dopant distributions, and methods of forming integrated assemblies

Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have primary regions of a first vertical thickness, and have terminal projections of a second vertical thickness which is greater than the first vertical thickness. The terminal projections include control gate regions. Charge-blocking regions are adjacent the control gate regions, and are vertically spaced from one another. Charge-storage regions are adjacent the charge-blocking regions and are vertically spaced from one another. Gate-dielectric material is adjacent the charge-storage regions. Channel material is adjacent the gate dielectric material. Some embodiments included methods of forming integrated assemblies.

Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

Growing community of inventors

Boise, ID, United States of America

Shyam Surthi