Tokyo Electron Limited

Shyam Sridhar

Alok Ranjan

Sergey Alexandrovich Voronin

Peter Lowell George Ventzek

Christopher Talone

Mitsunori Ohata

Hiroto Ohtake

Yusuke Yoshida

Ya-Ming Chen

Andrew Nolan

Li Wang

Michael Hummel

Christopher Catano

Nathaniel C Cady

Sang Cheol Han

Erdinc Karakas

Caitlin Philippi

Karsten Beckmann

Martin Rodgers

Qi Wang

Nayoung Bae

Qiang Wang

According to an embodiment, a plasma processing system includes a plasma chamber, an RF source, a matching circuit, a balun, and a resonating antenna. The resonating antenna includes a first and a second spiral resonant antenna (SRA), each having an electrical length corresponding to a quarter of a wavelength of a frequency of a forward RF wave generated by the RF source. The first end of the first SRA is coupled to a first balanced terminal of the balun and the second end of the first SRA is open circuit. The first end of the second SRA is coupled to a second balanced terminal of the balun and the second end of the second SRA is open circuit. The first and the second SRA are arranged in a symmetrically nested configuration having a same center point.

Balanced RF resonant antenna system

A method of processing a substrate that includes: loading the substrate in a plasma processing chamber, the substrate including an underlying layer; maintaining a steady state flow of a process gas into the plasma processing chamber in the plasma processing chamber; generating a plasma in the plasma processing chamber; exposing the substrate to the plasma to etch the underlying layer; and pulsing a first additional gas, using a first effusive gas injector, towards a first region of the substrate to disrupt the steady state flow of the process gas over the first region, the pulsing locally changing a composition of the plasma near the first region.

Method of uniformity control

A method of processing a substrate that includes: flowing a gas including a fluorocarbon to a plasma processing chamber; sustaining a plasma generated from the gas; depositing a carbonaceous layer over the substrate by exposing the substrate to the plasma, the substrate having a recess having an aspect ratio between 10:1 and 100:1, the depositing including a pulsed plasma process including: during a first time duration, setting a source power (SP) at a first SP level and a bias power (BP) at a first BP level, where the plasma includes fluorocarbon ions polymerizing on a bottom surface to form the carbonaceous layer, and during a second time duration, setting the SP at a second SP level higher than the first SP level and the BP at a second BP level lower than the first BP level, where the plasma includes fluorine radicals trimming the carbonaceous layer.

Topographic selective deposition

A plasma processing method includes generating a plasma within a processing chamber using source power to ignite a glow phase of the plasma, generating low-energy ions at a substrate supported by a substrate holder in the processing chamber from the plasma using lower-frequency radio frequency bias power applied during the glow phase, and generating high-energy ions at the substrate using higher-frequency radio frequency bias power applied during an afterglow phase of the plasma. The frequency of the higher-frequency radio frequency bias power is greater than the frequency of the lower-frequency radio frequency bias power.

Plasma processing methods using multiphase multifrequency bias pulses

Residue at the base of a feature in a substrate to be etched is limited so that improved profiles may be obtained when forming vertical, narrow pitch, high aspect ratio features, for example fin field effect transistor (FinFET) gates. A thin bottom layer of the feature is formed of a different material than the main layer of the feature. The bottom material may be comprised of a material that preferentially etches and/or preferentially oxidizes as compared to the main layer. The bottom layer may comprise silicon germanium. The preferential etching characteristics may provide a process in which un-etched residuals do not remain. Even if residuals remain, after etch of the feature, an oxidation process may be performed. Enhanced oxidation rates of the bottom material allow any remaining residual to be oxidized. Plasma oxidation may be used. The oxidized material may then be removed by utilizing standard oxide removal mechanisms.

Method for gate stack formation and etching

The performance of a ReRAM structure may be stabilized by utilizing a dry chemical gas removal (or cleaning) process to remove sidewall residue and/or etch by-products after etching the ReRAM stack layers. The dry chemical gas removal process decreases undesirable changes in the ReRAM forming voltage that may result from such sidewall residue and/or etch by-products. Specifically, the dry chemical gas removal process may reduce the ReRAM forming voltage that may otherwise result in a ReRAM structure that has the sidewall residue and/or etch by-products. In one embodiment, the dry chemical gas removal process may comprise utilizing a combination of HF and NHgases. The dry chemical gas removal process utilizing HF and NHgases may be particularly suited for removing halogen containing sidewall residue and/or etch by-products.

Methods for resistive RAM (ReRAM) performance stabilization via dry etch clean treatment

In one example, a method of processing a substrate includes receiving a substrate in a processing chamber, the substrate having an etch mask positioned over an underlying layer to be etched, where the underlying layer is a silicon-containing layer. The method includes executing a first etch process that includes forming a first plasma from a first process gas that includes hydrogen bromide or chlorine and etching the underlying layer using products of the first plasma. The method includes executing a second etch process that includes forming a second plasma from a second process gas that includes fluorine and etching the substrate using products from the second plasma. The method may include alternating between the first etch process and the second etch process.

Plasma etch processes

Sidewall etching of substrate features may be achieved by employing an etch stop layer formed over the features. The etch stop layer is thinner on sidewalls of the features as compared to the bottom of the features. The lateral etching of the features is achieved by use of an over etch which breaks through the etch stop layer on the sidewalls of the features but does not break through the etch stop layer formed at the bottom of the features. The use of the etch stop layer allows for lateral etching while preventing unwanted vertical etching. The lateral etching may be desirable for use in a number of structures, including but not limited to 3D structures. The lateral etching may also be used to provide vertical sidewalls by reducing the sidewall taper angle.

Method to achieve a sidewall etch

A method of etching is described. The method providing a substrate having a first material composed of silicon-containing organic material and a second material that is different from the first material, forming a chemical mixture by plasma-excitation of a process gas containing SFand an optional inert gas, controlling a processing pressure at or above 100 mtorr, and exposing the first material on the substrate to the chemical mixture to selectively etch the first material relative to the second material.

Method of plasma etching of silicon-containing organic film using sulfur-based chemistry

Methods and systems for selective silicon anti-reflective coating (SiARC) removal are described. An embodiment of a method includes providing a substrate in a process chamber, the substrate comprising: a resist layer, a SiARC layer, a pattern transfer layer, and an underlying layer. Such a method may also include performing a pattern transfer process configured to remove the resist layer and create a structure on the substrate, the structure comprising portions of the SiARC layer and the pattern transfer layer. The method may additionally include performing a modification process on the SiARC layer of the structure, the modification converting the SiARC layer into a porous SiARC layer. Further, the method may include performing a removal process of the porous SiARC layer of the structure, wherein the modification and removal processes of the SiARC layer are configured to meet target integration objectives.

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Albany, NY, United States of America

Shyam Sridhar