Cirrus Logic Inc.

Silicon Laboratories Inc.

Nxp B.v.

St-Ericsson Sa

Crystal Semiconductor Corporation

Cirrlus Logic, Inc.

Shyam S Somayajula

Xiaoyu Xi

Xue-Mei Gong

Wenjung Sheng

Karl Ernesto Thompson

John L Melanson

Donald A Kerth

Rahul Singh

Ammisetti Prasad

Tod Paulus

Ahsan Habib Chowdhury

James Antone

Daniel O Gudmundson

Daniel Gudmondson

Tony G Mellissinos

Ammisetti V Prasad

John Laurence Melanson

In one embodiment, a power supply switching circuit may automatically provide power to a clock circuit from one of an auxiliary power supply and a main power supply, based on a voltage of the main power supply. To provide automatic switching, a switch circuit coupled between the power supplies and the clock circuit may be controlled by a voltage detector, in some embodiments.

Automatically switching power supply sources for a clock circuit

A wireless system includes a radio and a voltage regulator, which provides a supply voltage to the radio. The voltage regulator includes a storage element, at least one switch that is coupled to the storage element and a controller. The controller operates the voltage regulator in a continuous mode of operation, operates the voltage regulator in a discontinuous mode of operation in response to an output current of the voltage regulator decreasing below a predetermined threshold; operates the switch(es) to energize the storage element in response to a detection of whether an output voltage is below a threshold level; operates the switch(es) to halt the energization of the storage element in response to detecting a current in the storage element reaching a predetermined current threshold; operates the switch(es) to energize and de-energize the storage element in the discontinuous mode of operation; and operates the switch(es) to energize the storage element in synchronization with a periodic clock signal.

Controlling a voltage regulator

A system includes a sampler to sample an input voltage and a switching regulator. The switching regulator is adapted to regulate a switching operation of the regulator in response to the sampling by the sampler.

Management of regulator-induced switching noise for sampled systems

A technique includes energizing a storage element of a voltage regulator in response to the detection of an output voltage of the voltage regulator falling below a threshold level. The technique includes halting the energization of the storage element in response to the detection of a current in the storage element reaching a predetermined threshold.

A system includes a digital circuit that may be clocked by a digital clock signal having an associated clock period. The system also includes a sample clock generation circuit coupled to a sampling circuit. The sample clock generation circuit may be configured to receive an input clock having a fixed phase relationship with respect to the digital clock signal. The sample clock generation circuit may also generate a sample clock having a first sampling edge corresponding to a first relative offset within the clock period and a subsequent sampling edge corresponding to a different relative offset within the clock period. The sampling circuit may be configured to sample a designated signal upon a first sampling instance corresponding to the first sampling edge and to sample the designated signal upon a subsequent sampling instance corresponding to the subsequent sampling edge.

Method and system for sampling a signal

In one embodiment, the present invention includes methods and apparatus for providing initial control values to programmable load capacitors of an oscillator, such as that of a real time clock circuit. Using the initial values, the real time clock circuit may begin operation, enabling additional circuitry within an integrated circuit to begin operation. This additional circuitry may cause operating values to program the load capacitors to provide a desired reference clock based on a given system's requirements.

Clock circuit with programmable load capacitors

A system in which drooping of the video levels due to leakage currents and proper DC bias level is addressed by providing a charge into the video signal to offset the leakage currents and to provide DC bias. To determine the leakage current level, measurements are made measuring the voltages of the syncs and the blanking intervals. To determine the DC bias, a measurement is made of the sync. Over a series of video lines these measurements are averaged. If the average is below the desired level, a charge is provided via a current source to the incoming signal. By having the current source provide charge during each video line, droop is reduced and the proper DC bias is provided.

Method and apparatus to interface video signals to a decoder to compensate for droop

A wireless communication device is disclosed that provides a sidetone to the device user. The device converts an outbound analog audio signal to an outbound audio bitstream from which a sidetone bitstream is extracted. The device also converts an inbound digital audio signal to an inbound audio bitstream. A filter in the device both adds the sidetone bitstream to the inbound audio bitstream and filters the resultant added bitstreams to provide an analog audio signal with sidetone.

Method and apparatus for providing a sidetone in a wireless communication device

A video decoder in which 1) resolution quality can be improved for a given bit count analog-to-digital converter, 2) a lower bit count analog-to-digital converter can be used with substantially similar quality or 3) a combination of improved resolution quality with a lower bit count analog-to-digital converter can be done. In the preferred embodiment, a DC bias is added to the video signal after the sync portion of the composite signal has been received and prior to the active video being received. This bias is then removed after the end of the active video period. By applying this bias, the DC voltage level of the video signals is actually reduced, so that the full scale value of the analog-to-digital conversion process can also be reduced. Thus, compared to using an unbiased signal, increased A/D converter resolution is obtained. In an alternative embodiment, the sync portion can be biased upwardly during the front porch and then be returned during the back porch.

Method and apparatus to improve ADC dynamic range in a video decoder

A delta sigma modulator is provided. The delta sigma modulator comprises quantitizer circuitry configured to generate a digital signal using a first analog signal and dither control circuitry configured to use the digital signal to adjust an amount of dither applied to the first analog signal.

System and method for adjusting dither in a delta sigma modulator

A sample and hold circuit including a sampling capacitor for storing a sample of an input signal, an output stage for outputting the sample stored on the sampling capacitor; and input circuitry for sampling the input signal and storing the sample on the sampling capacitor. The input circuitry includes an autozeroing input buffer which selectively samples the input signal during a first operating phase and holds a sample of the input signal during a second operating phase. The autozeroing input buffer cancels any offset error. The input circuitry also includes switching circuitry for selectively coupling the sampling capacitor with an input of the sample and hold circuitry during the second operating phase and to an output of the autozeroing input buffer during the first operating phase.

Sample and hold circuits and methods with offset error correction and systems using the same

Metastable compensation circuitry for detecting and compensating for metastable states of a regenerative latch in a charge redistribution analog to digital converter First and second latches each having a selected threshold voltage for monitor corresponding first and second outputs of regenerative latch Detection logic detects a selected output state of the first and second latches corresponding to a metastable state of regenerative latch Suppression logic generates an output of a selected logic level in response to the detection of a metastable state by detection logic

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Austin, TX, United States of America

Shyam S Somayajula