Freescale Semiconductor,inc.

Shyam S Gupta

Chetan Verma

Amit Roy

Vijay Tayal

Nipun Mahajan

Deepak Jindal

Ajay K Gaite

Ajay Kumar

Sahil S Dabare

Amar Nath N Deogharia

A system and method for determining power leakage of an electronic circuit design that includes a plurality of digital logic elements, using an electronic design automation (EDA) tool that includes a processor and an automatic test pattern generation (ATPG) tool for generating multiple sets of input value strings. The ATPG tool generates test patterns that include input value strings for simulating each digital logic element of the circuit design independently. A mapping between generated output values and corresponding input values is stored in a look up table (LUT). Thereafter, the ATPG tool generates test patterns that include input value strings for simulating the real-time behavior of the circuit design. The processor determines power leakage of the circuit design based on probability of occurrence of each unique input value string at the input of each digital logic element and corresponding predetermined power leakage values.

System and method for determining power leakage of electronic circuit design

An integrated circuit with a single-channel input/output (I/O) interface and a multi-channel I/O interface includes functional circuits that operate in different clock domains and a test circuit. For a single-channel I/O interface, the test circuit simulates read/write operations by bypassing the functional circuits and performs electrical characterization of the single-channel I/O interface. For a multi-channel I/O interface, the test circuit configures a plurality of channels of the multi-channel interface in a half-duplex mode and performs electrical characterization using data loop back by bypassing the functional circuits.

System for performing electrical characterization of asynchronous integrated circuit interfaces

A system on a chip (SOC) includes a physical interface having first and second sets of interface pads. Interface pads from the first set are interleaved with interface pads from the second set. Additionally, the SOC is arranged for operation with a superset die having first and second personalities and has a physical interface with interface pads. The SOC uses a first number of interface pads in the first personality and a second number of interface pads in the second personality, where the first number is greater than the second number. A switch switches signals between the superset die and the physical interface and, in the second personality, switches signals to the physical interface so that interface pads in the second number of interface pads are interleaved with interface pads not in use in the second personality.

System on a chip with interleaved sets of pads

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Noida, India

Shyam S Gupta