International Business Machines Corporation

Shyam Ramji

Gi-Joon Nam

Paul Gerard Villarrubia

Natarajan Viswanathan

Charles Jay Alpert

Myung-Chul Kim

Alexander Joel Suess

Taraneh Taghavi

Lakshmi Narasimha Reddy

Randall J Darden

David James Hathaway

Zhuo Li

Christopher J Berry

Nathaniel Douglas Hieter

Benjamin Neil Trombley

Sourav Saha

Gustavo Enrique Tellez

Jarrod Alexander Roy

Chin Ngai Sze

Eddy St Juste

Hua Xiang

Timothy A Schell

Arjen Alexander Mets

Ajith Kumar M Chandrasekaran

Zahi M Kurzum

Matthew D Affeldt

Ravi Nair

Hong Min

Ruchir Puri

Petr Novotny

Diwesh Pandey

Haoxing Ren

Motohiro Kawahito

Joachim Keinert

Qi Zhang

Takuya Nakaike

Lei Yu

Salim Ahmed Shah

Jinwook Jung

Joseph J Palumbo

Douglass T Lamb

Yiu-Hing Chan

Andrew D Huber

Frank Musante

Cindy ShuiKing Washburn

Michael W Dotson

David John Geiger

Rokesh Jayasundar

Adam R Jatkowski

Mark D Mayo

William R Migatz

David W Lewis

Ari Freund

Edward F Mark

Rongjian Liang

John L McCann

Bella Dubrov

Haggai Eran

Ashish K Singh

Design rule violations ('DRVs') may be predicted using a design rule check (“DRC”) density map during a physical synthesis operation prior to executing a routing operation.

Rule check heatmap prediction

Techniques for refinement of data pipelines are provided. An original file of serialized objects is received, and an original pipeline comprising a plurality of transformations is identified based on the original file. A first computing cost is determined for a first transformation of the plurality of transformations. The first transformation is modified using a predefined optimization, and a second cost of the modified first transformation is determined. Upon determining that the second cost is lower than the first cost, the first transformation is replaced, in the original pipeline, with the optimized first transformation.

Streamlining data processing optimizations for machine learning workloads

A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.

Memory element graph-based placement in integrated circuit design

A method includes receiving a source file specifying circuit components and electrical connections therebetween. At least a portion of the circuit components and electrical connections are within one or more of a set of logical hierarchical groupings, and a given one of the groupings has one or more electrical connections to at least another one of the groupings. The method also includes selecting an initial subset of the groupings based on one or more characteristics of respective ones of the set of groupings and performing individual logical optimization of respective ones of the initial subset. The method further includes determining a revised subset based on the one or more characteristics of the respective ones of the set of groupings as modified by the logical optimization, and performing global physical optimization of the circuit components and electrical connections based at least in part on the revised subset.

Hierarchy-driven logical and physical synthesis co-optimization

A design system accesses at least one placement template for at least one structured soft block composed of a pre-defined set of cells with relative placement information for the pre-defined set of cells. The design system optimizes implementation of the at least one structured soft block by propagating constants while preserving relative placement structure of the pre-defined set of cells within each at least one structured soft block according to the respective at least one placement template accessed for the at least one structured soft block.

Propagating constants of structured soft blocks while preserving the relative placement structure

Techniques regarding functional placement of one or more logic gates in a periodic circuit row configuration are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an optimization component, operatively coupled to the processor, that can determine functional placement of a logic gate in a self-aligned double patterning process that can form a periodic circuit row configuration.

Autonomous placement to satisfy self-aligned double patterning constraints

A system and method of performing model-based refinement of a placement of components in integrated circuit generation select one of the components as a candidate component and postulate a move of the candidate component from an original position to a new position. The method includes defining nets associated with the candidate component. An initial perimeter and a new perimeter associated with each of the one or more nets are defined. The initial perimeter includes the candidate component at its original position and the new perimeter includes the candidate component at its new position. The method includes quantifying a change from the initial perimeter and the new perimeter and the original position and the new position, and obtaining a model of wires interconnecting the candidate component to the components of each of the nets. A result of the placement is provided for manufacture of the integrated circuit.

Model-based refinement of the placement process in integrated circuit generation

The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.

Large cluster persistence during placement optimization of integrated circuit designs

The performance of a computer performing electronic design analysis is improved by representing a putative circuit design as a set of movable blocks of predetermined size which must fit into a bounding box (said blocks include a plurality of subsets to be interconnected by wires) and initially placing the set of blocks by quadratic initialization. Each of the blocks has first and second coordinates and weights are assigned to nets connecting those of the blocks within the subsets, the quadratic initialization in turn includes determining a cost of each of the nets connecting any two of the blocks within the subsets as one-half of a sum of squares of distances between the any two of the blocks; and minimizing a total cost over all of the nets to determine an initial placement of the set of blocks. Analytical placement is then carried out based on the initial quadratic placement.

Enhancing stability of half perimeter wire length (HPWL)-driven analytical placement

A physical synthesis system includes a path straightening module, an ideal critical point identification (ID) module, and a free-space ID module. The path straightening module identifies at least one meandering critical path of a circuit, and generates a reference curve based on dimensions of the critical path. The ideal critical point ID module identifies at least one critical point on the reference curve. The free-space ID module identifies at least one free-space to receive a gate with respect to at least one critical point. The physical synthesis system further includes a free-space selector module and a gate modification module. The free-space selector module determines a modified slack timing value based on relocating the gate to the at least one free-space. The gate modification module moves the gate to the at least one free-space when the modified slack timing value is greater than an initial slack timing value.

Critical path straightening system based on free-space aware and timing driven incremental placement

A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.

Optimizing placement of circuit resources using a globally accessible placement memory

A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.

Hierarchically aware interior pinning for large synthesis blocks

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Lagrangeville, NY, United States of America

Shyam Ramji