Samsung Electronics Co., Ltd.

Apple Inc.

Shy Hamami

Yoel Yaffe

Amit Eisenberg

Pradeep R Trivedi

Gal Bitan

Fabien S Faure

Uzi Hizi

Roee Elizov

Oded Monzon

Yair Itzhak

Huaimin Li

Guy Horowitz

Yaron Cohen

Shahaf Duenyas

Yoav Piepsh

A method performed with an image sensor having a pixel array. At least one frame of a scene may be obtained using the pixel array. At least one region of interest (ROI) is identified within the frame. Subsequent frames of the scene are obtained, which involves controlling the pixel array to perform high resolution imaging with respect to the at least one ROI and low resolution imaging using analog binning with respect to remaining regions of the frames.

Image sensor employing varied intra-frame analog binning

An image sensor may include control circuitry, a plurality of pixels, and an image processor. Each pixel includes a photodetector, at least first and second storage nodes, and transfer circuitry. The transfer circuitry is responsive to control signals generated by the control circuitry to transfer first charges generated by the photodetector during a first exposure time within a frame period to the first storage node. Second charges may be generated by the photodetector during a second, longer exposure time during the frame period, and transferred to the second storage node. The image processor may generate image frame data based on output voltage samples derived from the first and second charges of each of the plurality of pixels.

HDR image sensor employing multi-tap pixel architecture and method for operating same

An apparatus includes an oscillator circuit, a counter circuit, and a control circuit. The oscillator circuit may receive an input clock signal and an inverse input clock signal, and, for a first time period, may generate an oscillator output signal with a frequency based on a duty cycle of the input clock signal. For a second time period, the oscillator circuit may generate the oscillator output signal with a frequency based on a duty cycle of the inverse input clock signal. The counter circuit may count oscillations of the oscillator output signal over the first time period and over the second time period. The control circuit may determine, based on the oscillations counted by the counter circuit during the first time period and the second time period, a duty cycle value indicative of the duty cycle of the input clock signal.

Digital on-chip duty cycle monitoring device

A counter circuit for an analog to digital converter includes: a plurality of counter stages configured to obtain an integer multiple of a digital gain for the analog to digital converter by bypassing at least one of the plurality of counter stages. An analog-to-digital converter includes at least one counter circuit, and an image sensor includes the analog-to-digital converter, which includes the counter circuit.

Counter circuits, analog to digital converters, image sensors and digital imaging systems including the same

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Ganei-Tikva, Israel

Shy Hamami