Integrated Device Technology, Inc.

Advanced Micro Devices Corporation

Renesas Electronics America Inc.

Globalfoundries Inc.

Shwetal Arvind Patel

Chenxiao Ren

Alejandro F Gonzalez

Andy Zhang

Wen Jie Meng

Dale E Gulick

Mark Douglas Hummel

Larry David Hewitt

Frederick Daniel Weber

Gerald Robert Talbot

Glenn A Dearth

R Stephen Polzin

Paul C Miranda

Richard W Reeves

Ross Voigt La Fetra

In an embodiment, an apparatus is disclosed that includes a memory slot including a certificate chain corresponding to an entity and a memory block. The memory block has protection enabled. The apparatus includes a processing device. The processing device is configured to receive a request message to clear protection for the memory block from a computing device of the entity. The request message includes a signature generated based at least in part on a private key of the entity. The processing device is configured to determine a public key corresponding to the entity based at least in part on the certificate chain, determine that the signature is valid based at least in part on the public key, determine that the protection for the memory block corresponds to the certificate chain and clear the protection for the memory block.

Write protect function with secure certificate authentication

An apparatus includes a plurality of registers and a host interface comprising a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry to a low power state. One of the plurality of pins may be an enable pin. The apparatus may be configured to enter the low power state in response to setting the power state entry register to a first value and providing the enable pin a signal with a first level. The apparatus may be configured to exit the low power state in response to providing the enable pin the signal with a second level. The apparatus may enter an idle state after exiting the low power state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control a status of a plurality of regulators.

DDR5 client PMIC power up sequence and state transitions

An apparatus including a host interface and a registered clock driver interface. The host interface may be configured to receive an enable command from a host. The registered clock driver interface may be configured to perform power management for a dual in-line memory module, generate data for the dual in-line memory module, communicate the data, receive a clock signal and communicate an interrupt signal. The registered clock driver interface may be disabled at power on. The registered clock driver interface may be enabled by in response to the enable command. The apparatus may be implemented as a component on the dual in-line memory module.

DDR5 RCD interface protocol and operation

An apparatus including a host interface and a power management interface. The host interface may be configured to receive control words from a host. The power management interface may be configured to (i) enable the host to read/write data from/to a power management circuit of a dual in-line memory module, (ii) communicate the data, (iii) generate a clock signal and (iv) communicate an interrupt signal. The power management interface is disabled at power on. The apparatus is configured to (i) decode the control words, (ii) enable the power management interface when the control words provide an enable command and (iii) perform a response to the interrupt signal. The clock signal may operate independently from a host clock.

DDR5 PMIC interface protocol and operation

A register clock driver for a DDR5 memory is presented. A register clock driver (RCD) can include a logic having one or more input channels, each of the one or more input channels receiving input signals; and a plurality of ranked output ports associated with each of the one or more input channels, the logic providing the input signals received on each of the one or more input channels to the associated plurality of ranked output ports according to control signals. The RCD can operate in a default mode, wherein input signals from the input channels are output to both of the output ports associated with that channel, or can operate in a non-default mode where input signals from the input channels are sent to the appropriate ranked output port associated with that channel. In either case, unused signaling on the output ports is held high.

Register clock driver for DDR5 memory

Operation of an Enhanced Data Buffer and Intelligent NV Controller for Simultaneous DRAM and Flash Memory Access has been disclosed. In one implementation a host can operate at full DRAM speed to a DIMM having thereon a NV Controller, DRAM, and flash memory.

Enhanced data buffer and intelligent NV controller for simultaneous DRAM and flash memory access

An apparatus includes a transmitter and a controller. The transmitter may be configured to transmit data stored in a memory. The controller may be configured to (i) train one or more transmit parameters of the transmitter to synchronize transmission of the data with a clock signal while in a first mode, (ii) save the transmit parameters in response to a command received while the transmitter is in the first mode, and (iii) configure the transmitter to transmit the data while in a second mode using the transmit parameters as learned while in the first mode.

Synchronization of data transmission with a clock signal after a memory mode switch

An apparatus includes a memory and a circuit. The memory may have a transmitter. The memory may be configured to (a) train transmit parameters of the transmitter that synchronize transmission of data with a clock signal while in a first mode, (b) save the transmit parameters in response to a command received while in the first mode, and (c) transmit additional data while in a second mode using the transmit parameters learned while in the first mode. The circuit may have a receiver in communication with the memory. The circuit may be configured to (a) train receive parameters of the receiver that synchronize reception of the data with the clock signal while the memory is in the first mode and (b) receive the additional data from the memory while the memory is in the second mode using the receive parameters learned while the memory was in the first mode.

Memory includes transmitter for data synchronization transmission after a mode switch and method thereof

An apparatus includes a plurality of data lines defining a data bus for communicating data. A controller is operable to communicate a plurality of data transfers over the data bus using a plurality of data time slots, wherein for at least a subset of the data time slots the controller is operable to communicate an associated data bus inversion indicator indicating that bits communicated during the associated data time slot are inverted, the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and the controller is operable to communicate a global data bus inversion indicator indicating an inversion of the data bus inversion vector.

Reducing simultaneous switching outputs using data bus inversion signaling

A technique reduces cost, complexity and/or power consumption of a memory system by including intelligence in a memory buffer circuit of the memory system. An apparatus includes a memory buffer circuit configured to selectively operate in one of a plurality of modes. In a first mode, the memory buffer circuit is configured to interface to a first type of memory device, is configured to enable an input circuit of the memory buffer circuit, and is configured to drive on a terminal of a memory interface of the memory buffer circuit a version of a signal received by the input circuit during a memory operation. In a second mode, the memory buffer circuit is configured to interface to the first type of memory device, is configured to disable the input circuit, and is configured to drive a signal on the terminal during the memory operation.

Intelligent memory buffer

A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

System including a host connected to a plurality of memory modules via a serial memory interconnect

A memory device may be implemented to respond to and one or more command encodings that specify different burst lengths than the burst length indicated by the current burst length setting for the memory device. For example, a memory device may include a memory array and a mode register configured to store a value indicating a current burst length. The memory array may be configured to perform a first burst access having a first burst length in response to receiving a first command encoding and to perform a second burst access having a second burst length, which does not equal the current burst length, in response to receiving a second command encoding. A memory controller may be implemented to generate to and one or more command encodings that specify different burst lengths than the burst length indicated by the current burst length setting for a targeted memory device.

Growing community of inventors

San Jose, CA, United States of America

Shwetal Arvind Patel