Nec Corporation

Fujitsu Corporation

Nippon Telegraph and Telephone Public Corporation

Nippon Electric Co., Ltd.

Shuzo Tsugane

Naoki Mukawa

Hideo Kuroda

Mitsuo Nishiwaki

Kiichi Matsuda

Makoto Hiraoka

Tooru Yasuda

Yasushi Sano

Sadaharu Hiratsuka

Toshio Kawaji

In a digital video communication system, a network clock source is provided to supply a common clock pulse synchronized with the transmission speed of the system to each station through a transmission channel to allow it to derive a video sync pulse. This sync pulse is applied to a video signal source to generate an analog composite television signal. A quantization sampling pulse is derived from the video sync pulse which is contained in the composite television signal to quantize the composite television signal. The quantized video signal is stored in a buffer and forwarded to a receiver station in response to the received network clock pulse, so that the quantization sampling rate and the transmission sampling rate of a transmitter station of the system are synchronized with each other. The sampling rate of the dequantization process at the receiver station is also synchronized with the transmission sampling rate.

Digital video communication system having a network clock source

A television conference system includes, in a transmitting side, a plurality of TV cameras assigned with camera ID codes, and in a receiving side, a plurality of TV monitors assigned with monitor ID codes and frame memories for storing inputs to the TV monitors. In the transmitting side, a moving picture signal output from a TV camera selected by a camera ID number is encoded, and the encoded moving picture signal together with a monitor ID code of a TV monitor designated to display an output from the selected TV camera are transmitted to the receiving side. In the receiving side, writing is performed in a frame memory corresponding to the TV monitor designated by the monitor ID signal to display a moving picture on the TV monitor, writing in each of the frame memories corresponding to the other TV monitors is inhibited and the last frame of the latest moving picture displayed thereon is displayed as a still picture, and selection of the TV camera and designation of the TV monitor are arbitrarily performed.

Television conference system including many television monitors and

An inter-frame encoding/decoding equipment for television signals consists of inter-frame encoding equipment encoding a difference between television signals and the output of a frame memory and inter-frame decoding equipment which receives an encoded signal sent from the inter-frame encoding device via a transmission line, which decodes by adding the output of the frame memory to the encoded signal. The inter-frame encoding equipment is provided with a first operation circuit which operates the remainders obtained by dividing, by a predetermined value, the number of bits of logic '1' in the bit groups into which the output or the input of the frame memory is divided by a predetermined unit. The inter-frame decoding equipment is provided with a second operation circuit which operates the remainders obtained by dividing, by a predetermined value, the number of bits of logic '1' in the bit groups into which the output or the input of the frame memory is divided by a predetermined unit. The inter-frame decoding equipment is further provided with a comparator circuit which compares and checks the values operated by the first and the second operation circuits to detect a transmission error.

System for detecting a transmission error

A video signal frame memory is refreshed without requiring either a separate transmission line or the transmission of bursts of data. This is done by dividing the frame signals into blocks of data, which are further divided into lines and sub-blocks. During each frame, refreshing signals are sent on a sub-block basis, thereby distributing the refreshing control signals and preventing many signals from being sent in bursts.

Method and arrangement for refreshing a frame memory in an interframe

Inter-frame encoding/decoding equipment for television signals includes inter-frame encoding equipment generating an encoded signal by encoding a difference between television signals and the output of a frame memory and inter-frame decoding equipment which receives the encoded signal sent from the inter-frame encoding device via a transmission line. The decoding equipment decodes by adding its output of the frame memory to the encoded signal. The inter-frame encoding equipment is provided with a first operation circuit which calculates remainders obtained by dividing a predetermined value, into bit groups of the output or the input of the frame memory. The inter-frame decoding equipment is provided with a second operation circuit which calculates remainders obtained by dividing, the predetermined value, into the bit groups of the output or the input of its frame memory. The inter-frame decoding equipment is further provided with a comparator circuit which compares and checks the remainders calculated by the first and the second operation circuits to detect a transmission error.

There is provided a code converting circuit for converting digital signals of fixed length codes into variable length codes and delivering a train of variable length codes produced by the conversion parallelly every predetermined K bits. The converting circuit comprises: a variable length code converter for converting an input fixed length code into a variable length code, sending the variable length code to an output signal line of K bits starting from a bit position next to that indicated by the output value of a first flip-flop, and sending an overflowing portion of the variable length code to an overlfow signal line; an adder with a modulo of K for adding the bit number of the variable length code corresponding to the input fixed length code to the output value of the first flip-flop; an OR circuit for receiving the output from the output signal line of the variable length code converter and the output from a second flip-flop; a switching circuit receiving the output signal of said OR circuit and the overflow signal from said variable length code converter and being responsive to a carry signal of the adder to selectively deliver as an output thereof one of the input signals; and a third flip-flop for storing the output signal of said OR circuit and delivering the stored value during the rise of the time slot following the delivery of the carry signal of the adder. The first flip-flop functions to delay the output value of the adder by one time slot and delivers the delayed output to the variable length code converter and the adder. The second flip-flop functions to delay the output signal of the switching circuit by one time slot and delivers the delayed output signal to the OR circuit.

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Tokyo, Japan

Shuzo Tsugane