Altera Corporation

Alters Corporation

Shuxian Chen

Jeffrey T Watt

Chun Lee Ler

Wilson Wong

Weiqi Ding

Yan Cui

Albert Ratnakumar

Jayakannan Jayapalan

Queennie Suan Imm Lim

Liping Li

Andy Louie Lee

Peter Smeys

Simardeep Maangat

Mark Chan

Fangyun Richter

Yowjuang (Bill) Liu

Bradley Jensen

Girish Venkitachalam

Yow-Juang (Bill) Liu

Deepa Ratakonda

Jeffrey T Wall

Mojy Curtis Chian

In one embodiment, a capacitor structure includes a substrate, a dielectric stack, a first conductor segment, a second conductor segment and a shielding conductor segment. The dielectric stack is formed on the substrate. A first layer of the dielectric stack includes a plurality of conductor segments routed only in a first direction. A first conductor segment among the multiple conductor segments may be biased to a first voltage. The second conductor segment among the multiple conductor segments may be biased to a second voltage. The shielding conductor segment may be biased to the second voltage and is formed at an end of the first conductor segment. In addition to that, the capacitances for the capacitor structure may be adjusted while the footprint of the capacitor structure is fixed.

Scalable fixed-footprint capacitor structure

An integrated circuit includes a buffer circuit, a receiving circuit, and a programmable repeater circuit. The programmable repeater circuit includes a routing input and an enable input. The programmable repeater circuit buffers an input signal received at the routing input from the buffer circuit through a first conductor to generate an output signal that is provided to an input of the receiving circuit through a second conductor only in response to an enable signal at the enable input enabling the programmable repeater circuit.

Programmable repeater circuits and methods

An integrated circuit package may include a substrate and an interposer. The interposer is disposed over the substrate. The interposer may include embedded switching elements that may be used to receive different power supply signals. An integrated circuit with multiple logic blocks is disposed over the substrate. The switching elements embedded in the interposer may be used to select a power supply signal from the power supply signals and may be used to provide at least one circuit block in the integrated circuit with a selected power supply signal.

Integrated circuit package with active interposer

Apparatus for integrated capacitors and associated methods are disclosed. In one embodiment, an integrated capacitor includes a first plurality of metal members that are fabricated using a first plurality of metal layers, and are oriented in a first orientation. The integrated capacitor also includes a second plurality of metal members that are fabricated using a second plurality of metal layers. The second plurality of metal members are oriented transverse to the first orientation. The integrated capacitor further includes a third plurality of metal members, which are fabricated using a third plurality of metal layers, and are oriented in the first orientation.

Apparatus and associated methods for capacitors with improved density and matching

In one embodiment, an integrated circuit is described. The integrated circuit includes a substrate, a dielectric stack, a first inductor and a second inductor. The dielectric stack may be formed above the substrate and includes first and second layers. The first inductor may be formed in both the first and second layers. The second inductor may also be formed in the first and second layers with a substantial portion of the first inductor structure overlaps with the second inductor structure.

Interleaved T-coil structure and a method of manufacturing the T-coil structure

An integrated circuit system, and a method of manufacture thereof, includes: an integrated circuit substrate; and a discretized tunable precision resistor having a total resistance including: a resistor body over the integrated circuit substrate, interconnects directly on the resistor body, metal taps directly on the interconnects and at opposing sides of the resistor body, and conductive metal strips over the interconnects, wherein the total resistance is a function of an active resistor length of the resistor body between a pair of the metal taps in contact with two of the conductive metal strips.

Integrated circuit system with tunable resistor and method of manufacture thereof

An integrated circuit may include interconnects formed from alternating metal interconnect layers and inter-metal dielectric layers. A metal-insulator-metal capacitor may be formed within a selected inter-metal dielectric layer. The metal-insulator-metal capacitor may include first and second capacitor electrodes. The first capacitor electrode may contact a first conductive interconnect line in an underlying metal interconnect layer. The second capacitor electrode may overlap the first capacitor electrode and a portion of a second conductive interconnect line in the underlying metal layer. A via may be formed between the underlying metal interconnect layer and an additional metal interconnect layer. The via may simultaneously contact the second capacitor electrode and the second conductive interconnect line.

Metal-insulator-metal capacitors between metal interconnect layers

A capacitor structure having a complete terminal shield is provided. The capacitor structure may include a first conductive segment with a first set of conductive fingers and a second segment structure with a second set of conductive fingers. The second set of conductive fingers may be spatially interleaved with the first set of conductive fingers in the first conductive structure. The first conductive segment may receive a first voltage, whereas the second conductive segment may receive a second voltage that is different than the first voltage. The capacitor structure further includes a conductive shielding structure that is connected to the first conductive segment. The conductive shielding structure may laterally surround the second conductive segment from at least three sides. An additional conductive shielding structure that connects to the first and second conductive segments is formed directly above the first and second conductive segments.

Methods and apparatus for fabricating capacitor structures with a terminal shield

An inductor may be formed from a conductive path that includes intertwined conductive lines. There may be two, three, or more than three intertwined conductive lines in the conductive path. The conductive lines may be formed from conductive structures in the dielectric stack of an integrated circuit. The dielectric stack may include metal layers that include conductive traces and may include via layers that include vias for interconnecting the traces. The intertwined conductive lines may be formed from the conductive structures in the metal and via layers. In crossover regions, the conductive lines may cross each other without electrically connecting to each other. Vias may be used to couple multiple layers of traces together to reduce line resistance.

Integrated circuit inductors with intertwined conductors

A metal-oxide-metal (MOM) capacitor structure is disclosed. The MOM capacitor includes a plurality of layers, each layer having a plurality of electrodes. The plurality of electrodes, separated by oxide layers, forms a first plate and a second plate of the MOM capacitor. The plurality of electrodes on each of the layers is coupled to a plurality of electrodes on an adjacent layer through a plurality of vias. A shield layer is coupled to each of the electrodes that forms the second plate of the MOM capacitor on each of the plurality of layers.

Shielded metal-oxide-metal (MOM) capacitor structure

A metal capacitor includes a plurality of interconnect segments. A first plurality of L-shaped fingers is driven to a first voltage level by a first interconnect segment. A second plurality of L-shaped fingers is driven to a second voltage level by a second interconnect segment. Each of the L-shaped fingers from a set of the first plurality of L-shaped fingers is adjacent to at least one of the L-shaped fingers from a set of the second plurality of L-shaped fingers.

Method and apparatus for implementing a metal capacitor with L-shaped fingers

A multiple gate semiconductor structure is disclosed having a thin segment of semiconductor with first and second major surfaces that are opposite one another, a first gate on the first major surface of the segment, a second gate on the second major surface of the segment opposite the first gate, a first differential input coupled to the first gate, and a second differential input coupled to the second gate. Preferably the semiconductor structure is symmetrical about a plane that extends through the thin segment between the first and second major surfaces. When a first voltage of a first polarity is applied to the first input and a second voltage of the same magnitude as that of the first voltage but of opposite polarity is applied to the second input, a virtual ground is established in the structure near its center of the segment.

Multiple gate semiconductor devices and their applications

A communications path may be formed from intertwined conductive paths. The intertwined conductive paths may be formed from one or more layers of conductive material in the dielectric stack of an integrated circuit. The dielectric stack may include metal layers, via layers, and a pad layer. The conductive paths may be formed from patterned conductive structures in the metal and pad layers. Vias in the via layers may be used to connect metal structures from multiple dielectric stack layers. The communications path may have segments in which the conductive paths run parallel to each other and may have cross-over regions in which the conductive paths cross one another without electrically connecting so that the paths twist about each other along their lengths. The communications path may be used to form a differential transmission line pair that distributes signals such as two-phase clock signals.

Intertwined pair of conductive paths arranged in a dielectric stack and having at least three metal layers

A first trimming capacitor having a first terminal and a second terminal is coupled in parallel between a first terminal and a second terminal of a first capacitor. The first trimming capacitor comprises a first plurality of switched capacitors having different capacitances coupled in parallel. Each of the switched capacitors comprises a switch capacitor and a switch coupled in series. In an illustrative application the first capacitor and the first trimming capacitor are coupled between an output terminal of an operational amplifier (op-amp) and an inverting input terminal of the op-amp. A second capacitor and a second trimming capacitor similar to the first capacitor and the first trimming capacitor are coupled between an input and the inverting input terminal of the op-amp.

Growing community of inventors

Fremont, CA, United States of America

Shuxian Chen