Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Akita Electronics Co., Ltd.

Hitachi Microcomputer System, Ltd.

Akia Electronics Co., Ltd.

Shuuichi Miyaoka

Masanori Odaka

Kazuhisa Miyamoto

Hiroshi Higuchi

Toshikazu Arai

Mitsugu Kusunoki

Michiaki Nakayama

Kouji Kobayashi

Takashi Ogata

Masato Ikeda

Katsumi Ogiue

Hideo Sawamoto

Masao Kato

Tsutomu Sumimoto

Kazuo Nakamura

Hisayuki Higuchi

Nobuo Tamba

Kenji Imai

A logic block of a memory (LSI) with logic functions includes RAM macrocells (RAMO-RAM7) and a centrally located gate array (GAO-GA5). Clock pulse shaping circuits (CSPO, CSP1) and input/output portion (I/O) surround the logic block. The logic block power supply includes a smoothing capacitor (CC) that is substantially the same size as a cell (GC) of the gate array. Each RAM macrocell has memory mats (MATOO-MAT21), word lines (WO-W127), data lines (DO-D7), and peripheral circuits (MPCOO-MPC21), which includes an address decoder and a sense amp (SAO). An input unit cell (ICO) receives ECL level signals and outputs ECL level signals (FIG. 5 ) and MOS level signals (FIG. 6 ). The input unit cells and analogous output unit cells (OCO) are selectively used singly or in parallel to accommodate signals of different form and driving capability. A wiring line replacement region (LRP) connects memory macrocell wiring lines with logic block wiring lines. A sequence control circuit cell or aligner (ALNO, ALN1) contiguous to the RAM macrocells transmits output signals to the logic block on the wiring lines. A clock signal distribution circuit (CDA) is arranged centrally of the RAM macrocells for distributing ECL level clock signals. The clock signal distribution circuit includes clock switch amplifier circuits (CSAO-CSA9) including bipolar transistors and MOSFETs (FIG. 23 ).

Semiconductor integrated circuit device

A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.

A logic circuit to be formed in a gate array is selected depending upon the value of the output load capacitance thereof, from among a CMOS circuit, a first Bi-CMOS circuit including an output bipolar transistor whose emitter size is set at a predetermined value, and a second Bi-CMOS circuit including an output bipolar transistor whose emitter size is larger than the emitter size of the output bipolar transistor of the first Bi-CMOS circuit. That is, the logic circuit is brought into a circuit form whose output load capacitance can be charged and discharged fastest. As a result, the logic circuit constructed in the gate array by adopting such a design technique has its operating speed raised. An improved structure is also provided for reducing wiring lengths by arranging bipolar transistors in adjacent basic cells to have mirror symmetry with one another. Further, particular gate width relationships are provided between MOSFETs within basic cells for reducing propagation delay and the required occupation area.

Semiconductor integrated circuit with bipolar transistors and MOSFETs

A semiconductor memory device is provided which includes a plurality of memory arrays each including main word lines, sub word lines to which a plurality of memory cells are connected, and a decoder which selectively connects the sub word lines to the main word lines. The main word lines are relatively short, since they are isolated electrically between memory arrays, and their resistance can thus be relatively low. The main word lines are not directly connected with a plurality of memory cells, and this results in a smaller capacitance coupled to the main word lines than is customarily the case. Consequently, the semiconductor memory device can have an enhanced operating speed.

Semiconductor memory device

A semiconductor memory device having a plurality of memory arrays in which static memory cells are disposed in a lattice arrangement at intersections of word lines and complementary data lines. The load circuits thereof are characterized as having a varying impedance effected by the combination of a first pair of P-channel MOSFETs disposed between the complementary data lines and a first node supplied with a first supply voltage and kept normally in an ON-state, and a pair of transistors, such as a second pair of P-channel MOSFETs, similarly connected as the first pair of P-channel MOSFETs and which are turned off selectively in accordance with a control signal corresponding to a predetermined selection timing signal in a write-in mode. The semiconductor memory device has a plurality of switching circuits which are coupled between the plurality of complementary data lines and a pair of data read and write lines. Each such switching circuit has a first pair of N-channel MOSFETs for selectively coupling the data input circuit of the memory device to a corresponding pair of complementary data lines via the pair of write data lines during a data write-in mode and a pair of P-channel MOSFETs for selectively coupling the corresponding pair of complementary data lines to the data output circuit via the pair of read data lines during the data read-out mode thereof.

A semiconductor integrated circuit is provided having first and second level generate circuits producing different levels and first and second emitter follower circuits respectively connected thereto. A level generated by one of the first and second level generate circuits is selectively supplied to either one of the first and second emitter follower circuits. This enables the first and second emitter follower circuits to supply the respective circuits formed in a semiconductor substrate with stable reference voltages.

Semiconductor memory

A semiconductor integrated circuit device includes a pulse width expander circuit for expanding the pulse width of a pulse signal of the ECL (emitter coupled logic) level that has a very narrow pulse width, a level conversion circuit for converting the output signal of the ECL level of the pulse width expander circuit into a CMOS (complementary metal oxide semiconductor) level, and an internal circuit that is so connected as to receive the output signal of the level conversion circuit. In other words, the pulse signal having a narrow pulse width is expanded to have a pulse width which is sufficient for the level conversion circuit prior to performing the level conversion operation. Therefore, the level of the pulse signals having narrow pulse widths is stably converted.

Write pulse signal generating circuit for a semiconductor memory device

In a semiconductor integrated circuit device having memory cell arrays, power source wirings are provided on the memory cell array in parallel with the long side of the memory cell array, thereby strengthening the power source wirings without increasing a chip size and planning reduction in power source impedances.

A high-speed bipolar MOS logic circuit is provided which includes a load resistance coupled between a first power supply voltage terminal and an output terminal and a bipolar transistor having a collector coupled to said output terminal and a base for receiving a predetermined voltage or an input signal a logic block is also provided including one or more MOSFETs having a source-drain path coupled in series between the emitter of said bipolar transistor and a second power supply voltage terminal.

High speed bipolar-MOS logic circuit including a series coupled

Semiconductor memory device with dual selection circuitry including CMOS

A semiconductor memory device having a plurality of memory arrays composed of mutually orthogonal row word lines and complementary column data lines, and static memory cells disposed in a lattice arrangement at the intersections of such word lines and complementary data lines; variable impedance load circuits having first P-channel MOSFETs disposed between the complementary data lines and a first supply voltage and kept normally in an on-state, and also having second P-channel MOSFETs connected in parallel with the first P-channel MOSFETs and cut off selectively in accordance with predetermined selection timing signals in a write mode; a plurality of signal generator circuits provided correspondingly to the memory arrays for forming the selection timing signals in accordance with write control signals and array selection signals, and then feeding the timing signals to the corresponding variable impedance load circuits; and a plurality of signal relay circuits provided correspondingly to a predetermined number of the signal generator circuits in such a manner that each signal relay circuit is disposed substantially at an intermediate position between the corresponding signal generator circuits, and transmitting to the corresponding signal generator circuits the write control signals obtained from the timing generator circuit TG. In this configuration, the signal transmitting paths between the timing generator circuit and the individual signal relay circuits are rendered mutually equivalent in length.

Growing community of inventors

Ohme, Japan

Shuuichi Miyaoka