Hitachi, Ltd.

Shutoku Watanabe

Yukimi Saiki

Masanori Ogino

Takashi Furuhata

Masanori Oguino

Sadao Kubota

A display device for information signals which performs highly efficient image display of a standard television signal, a high definition television signal, a progressive scanning television signal or a stereoscopic television signal on the same screen has a first signal input unit applied with the standard television signal, a second signal input unit applied with the high definition television signal, progressive scanning television signal or stereoscopic television signal, a mode designation unit for designating a mode for display of one of the signals, a signal conversion unit including a write unit for writing the first signal, at a frequency thereof, to memories and a read unit for reading the memories at a frequency which is nearly twice that of the first signal, a signal switching unit, a signal processing unit and a deflection switching unit, whereby a first display signal from the signal conversion unit or a second display signal from the second input terminal is selected and image-displayed on the same display unit through a deflection system. Through this, the cost of the device can be reduced, the standard television signal having less scanning lines can be displayed with substantially the same number of scanning lines as that of the high definition television signal, various kinds of disturbances can be eliminated to improve the image quality and a stereoscopic image can also be displayed.

Display device for information signals

A channel selection apparatus of a television receiver having a sequential shift signal input terminal for receiving a sequential shift signal to sequentially shift a selected channel position and an electronic tuning type channel selection IC having a defeat signal output terminal for producing a pulse output when the selected channel position changes and a plurality of channel selection output terminals for producing outputs indicative of the channels to be selected. The channel selection apparatus comprises a synchronizing signal discrimination circuit having a NAND gate and a charge/discharge circuit for detecting a synchronizing signal component appearing in a synchronizing signal separation circuit, a wave shaping circuit for producing a pulse output of a predetermined pulse width when triggered by the output at the defeat signal output terminal, and a NAND gate coupled to the synchronizing signal discriminating circuit, the wave shaping circuit and the sequential shift signal input terminal of the channel selection IC for producing a signal to sequentially shift the selected channel position by applying a signal to the sequential shift signal input terminal when the synchronizing signal discrimination circuit does not detect the synchronizing signal and the wave shaping circuit produces no output, and producing a signal to stop the sequential shift operation when the synchronizing signal discrimination circuit detects the synchronizing signal. This arrangement is particularly useful in selecting a channel which is receiving a broadcasting television station signal when the television receiver is turned on.

Channel selection apparatus for television receiver

In a television receiver having a peak value type AGC circuit for maintaining the amplitude difference between a carrier zero level and the peak value of a composite video signal amplified by a high frequency amplifier and a video intermediate frequency amplifier at a constant magnitude, an automatic brightness limiter (ABL) circuit is provided which controls the AGC circuit such that when the beam current exceeds a predetermined value and the carrier zero level approaches the peak value, a composite video signal of reduced amplitude is produced.

Automatic brightness limiter circuit

A noise reducing circuit for video signals, in which a transistor has its base connected to a video detector and its collector to a direct current source through a coil, two diodes have their cathodes connected together and grounded through a first resistor with the anode of one of the diodes connected to one end of the coil and that of the other diode connected to the other end thereof, the collector of the transistor is further connected through a capacitor and a second resistor to the input terminal of a video output amplifier, which input terminal is grounded through a third resistor, and the emitter of the transistor is connected through another coil to the said terminal and grounded through another capacitor and a variable resistor.

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Yokohama, Japan

Shutoku Watanabe