Semiconductor Components Industries, LLC

Shutesh Krishnan

Soon Wei Wang

Chee Hiong Chew

Jatinder Kumar

Erik Nino Mercado Tolentino

How Kiat Liew

Sw Wang

Ch Chew

Fui Fui Tan

Francis J Carney

Vemmond Jeng Hung Ng

Erik Nino Tolentino

Nurul Nadiah Manap

Yun Sung Won

Dennis Cadiz Yborde

Pui Leng Low

Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.

Semiconductor package and related methods

A method includes applying a sintering precursor material layer to each of a first surface and a second surface of a ceramic tile, and assembling a precursor assembly of a direct bonded copper (DBC) substrate by coupling a first leadframe on the sinter precursor material layer on the first surface of the ceramic tile and a second leadframe on the second surface of the sinter precursor material layer on a second surface of the ceramic tile such that the ceramic tile is disposed between the first leadframe and the second leadframe. The method further includes sinter bonding the first leadframe and the second leadframe to the ceramic tile to form a sinter bonded DBC substrate.

Direct bonded copper substrates fabricated using silver sintering

A system for attaching a terminal pin to a circuit trace on an electronic substrate. The system includes a sonotrode and a stage for holding the electronic substrate. The sonotrode is configured to direct ultrasound energy to a base region of the terminal pin placed on the circuit trace to weld the base region to the circuit trace. The system further includes a three-dimensional positioner coupled to the sonotrode. The three-dimensional positioner is configured to drive the sonotrode to lift the terminal pin from a rack and to place the terminal pin on the electronic substrate.

Bonding module pins to an electronic substrate

Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

Thin semiconductor package for notched semiconductor die

A method includes attaching semiconductor die to a carrier between copper pillars, covering with molding, backside grinding to expose first ends of the pillars and backside drain contacts of the die, and applying a layer of conductive material to electrically connect the first ends of the pillars and the backside drain contacts. The method further includes cutting grooves in the conductive material to isolate adjacent die, removing the carrier to expose second ends of the copper pillars in place in the molding, applying another layer of conductive material to electrically connect the second ends of the copper pillars and source contacts of adjacent die, singulating individual MCM packages each including a first die and a second die with a source of the first die connected to a drain of the second die via one of the copper pillars left in place in the molding.

Ultra-thin multichip power devices

A method includes disposing a terminal pin on an electronic substrate with a base region of the terminal pin in contact with a circuit trace on an electronic substrate, and ultrasonically coupling the base region of the terminal pin to the circuit trace.

A multi-chip module (MCM) includes a molded body portion having a first outer surface and a second outer surface. A conductive layer defines at least a portion of the first outer surface A conductive connection layer portion is disposed outside of the second outer surface of the molded body portion. A first semiconductor die and a second semiconductor die are disposed between the conductive layer and the conductive connection layer, and first molding portion is disposed between the first semiconductor die and the second semiconductor die. The first molding portion extends between the first outer surface and the second outer surface of the molded body portion. A conductive pillar is electrically coupled to the conductive layer defining at least a portion of the first outer surface and the conductive connection layer portion disposed outside of the second outer surface.

Thin semiconductor package and related methods

A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.

Bonding structure and method

An electronic device can include a packaging material having a first surface and a second surface opposite the first surface, and leads including die connection surfaces and external connection surfaces. The electronic device can further include a trench extending from an upper surface of the packaging substrate towards a lower surface of the packaging substrate, wherein a set of leads lie immediately adjacent to the trench, and the packaging material is exposed at the bottom of the trench. In an embodiment, an encapsulant is formed over the upper surface of the packaging substrate and within the trench. In a particular embodiment, the trenches may be formed before or after placing a die over the packaging substrate, or before or after forming electrical connections between the die and leads of the packaging substrate.

Electronic device including a packaging substrate having a trench

A connector assembly and a method for manufacturing the connector assembly. In accordance with embodiments, the connector assembly includes an electrical connector having first and second surfaces and first and second ends. A layer of electrically insulating material is formed from or on a portion of the first surface at the first end. Optionally, a layer of electrically insulating material can be formed from or on the second surface.

Growing community of inventors

Negeri Sembilan, Malaysia

Shutesh Krishnan