Semiconductor Components Industries, LLC

The Ritsumeikan Trust

Brillnics, Inc.

Shusuke Iwata

Isao Takayanagi

Shinichiro Matsuo

Shunsuke Okura

Shunsuke Tanaka

Takeshi Fujino

Masayoshi Shirahata

Mitsuru Shiozaki

Takaya Kubota

Hidenari Honda

Takeshi Kumaki

A solid-state imaging deviceincludes a pixel portionin which a plurality of pixels including photodiodes are arranged in rows and columns, a reading partfor reading pixel signals from the pixel portion, and a key generation partwhich generates a unique key by using at least one of pixel fluctuation information or reading part fluctuation information. According to this configuration, the tamper resistance of the unique key can be secured and consequently alteration and falsification of images can be prevented.

Solid-state imaging device, method for driving solid-state imaging device, and electronic apparatus with physically unclonable function

An image sensor may include an array of image pixels arranged in rows and columns. Each group of adjacent pixel columns may be coupled to a respective arithmetic memory circuit via corresponding analog-to-digital converter circuitry. The arithmetic memory circuit may include at least first, second, third, and fourth arithmetic units coupled in a chain. In some arrangements, only a subset of columns in each group of adjacent pixel columns is actively coupled to the arithmetic memory circuit. In other arrangements, all of columns in each group of adjacent pixel columns are actively coupled to the arithmetic memory circuit. The columns may be directly coupled to different arithmetic units in the arithmetic memory circuit to implement weighted horizontal binning or to the same arithmetic unit in the arithmetic memory circuit to implement flat horizontal binning.

Arithmetic memory with horizontal binning capabilities for imaging systems

An image sensor may include an array of image pixels arranged in rows and columns. Each image pixel arranged along a column may be coupled to a pixel column line. Each pixel column line may be coupled to column memory circuitry via a respective analog-to-digital converter circuit. The column memory circuitry may include multiple column memory circuits, including a spare column memory circuit. If none of the column memory circuits are defective, the spare column memory circuit is idle. If one of the column memory circuits is defective, the spare column memory circuit is engaged to bypass the defective column memory circuit. Configured in this way, the column memory circuitry is provided with column-wise memory repair capabilities.

Image sensors with column memory repair circuitry

An image sensor may include an array of image pixels arranged in rows and columns. Image pixels arranged along the same column may be coupled to a column line. The column line may be coupled to anti-eclipse control circuitry. In one suitable arrangement, the anti-eclipse control circuitry may include a data converter and an eclipse condition judgment circuit. The eclipse condition judgment circuit may be configured to record pixel output values at different points in time and to compare the recorded data to a predetermined threshold to determine whether an eclipse condition is satisfied. In another suitable arrangement, the anti-eclipse control circuitry may include a comparator and an eclipse condition judgment circuit. The comparator may compare a temporarily elevated pixel output value to a reference voltage to determine whether the eclipse condition is satisfied. In either arrangement, a maximum pixel level may be output when the eclipse condition is met.

Image sensors with anti-eclipse circuitry

Growing community of inventors

Tokyo, Japan

Shusuke Iwata