Fujitsu Corporation

Fujitsu Microelectronics Limited

Shusaku Yamaguchi

Atsushi Hatakeyama

Hiroyoshi Tomita

Toshiya Uchida

Hirohiko Mochizuki

Tadao Aikawa

Hiroyuki Kobayashi

Koichi Nishimura

Masato Takita

Yoshimasa Yagishita

Masaki Okuda

Yoshihide Bando

Shinya Fujioka

Satoshi Eto

Masato Matsumiya

Toshikazu Nakamura

Ayako Kitamoto

Kota Hara

Waichiro Fujieda

Mitsuhiro Higashiho

Hideki Kano

Masahiro Yada

A multipurpose terminal receives an address signal and a data signal. An address valid terminal receives an address valid signal indicating that a signal supplied to the multipurpose terminal is the address signal. An arbiter determines which of an external access request and an internal refresh request is given priority. The arbiter disables reception of the internal fresh request in response to a fact that both a chip enable signal and the address valid signal reach a valid level (an external access request). The arbiter enables the reception of the internal refresh request in response to completion of read or write operation. As a result, in a semiconductor memory device including the multipurpose terminal which receives the address signal and the data signal, contention between the read operation and the write operation, and a refresh operation which responds to the internal refresh request is prevented, which prevents a malfunction.

Semiconductor memory device including a terminal for receiving address signal and data signal

An electrical fuse circuit including: a capacitor composing an electrical fuse; a write circuit breaking an insulating film of the capacitor by applying voltage to between both terminals of the capacitor in accordance with a write signal; and a precharge circuit precharging with respect to the terminal of the capacitor, is provided.

Electrical fuse circuit, memory device and electronic part

A semiconductor memory device that includes an input buffer being inputted a write data from outside to buffer the write data and a control circuit putting the input buffer into an inactive state during a read operation and putting the input buffer into an active state when a read mask signal is inputted thereafter is provided.

Low current consumption semiconductor memory device

Semiconductor memory device with input buffer

A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

Semiconductor memory

A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.

A semiconductor memory device and information processing unit that improve speed at which data is written in a semiconductor memory device. A transfer section transfers data in a burst mode. A transferred number setting section sets the number of a plurality of bits of data transferred in the burst mode. A write command input section receives an input write command. A timing section measures time which has elapsed after the write command being input. A write start time setting section sets time which elapses before the writing of data being begun, according to the number of bits of data set by the transferred number setting section.

Semiconductor memory device and information processing unit

A semiconductor memory device includes a core area formed of memory blocks each having a relaxed sense amplifier arrangement, a data bus including data bus lines corresponding to the memory blocks, a plurality of input/output terminals provided in number corresponding to the data bus lines forming the data bus, and a data path switch circuit provided between the data bus the input/output terminals for providing interconnection paths between the input/output terminals and the data bus lines, wherein the data path switch circuit switches a part of the interconnection paths in response to a switch control signal such that the input/output terminals are connected respectively to predetermined memory cells located at respective, predetermined physical locations in any of the memory blocks.

Semiconductor memory device having a relaxed pitch for sense amplifiers

The present invention provides inside a scheduler a shift register, which performs a shift operation in synch with an external clock, or a clock generated thereby. Then, for example, when controlling latency from the supply of a command until the start of a column operation, at the time the command is supplied, a column access signal is stored in a shift register location, which corresponds to its latency. Because the shift register performs a shift operation in synch with a clock, a column access signal is outputted subsequent to a number of clock pulses, which correspond to its latency. A column control circuit, in response to the timing at which this column access signal is outputted, acquires a column address and other data required for a column circuitry operation, and starts a column circuitry operation. A configuration such as this simplifies the operation of the scheduler. In the above-described shift register, setting an internal operation command signal, which starts a prescribed internal operation, makes it possible to readily manage latency up until the start of an arbitrary internal operation.

Clock-synchronized memory device and the scheduler thereof

A latch circuit includes N data latch circuits to which N-bit parallel data are respectively applied where N is an integer, a data input control circuit setting the data latch circuits to a data input state in order, and a data output control circuit which controls the N data latch circuits to output, at different timings, latched data to M output terminals in the order of latch in the N data latch circuits where N.gtoreq.M.gtoreq.1.

Latch circuit, data output circuit and semiconductor device having the

A semiconductor memory device uses a wave pipeline system which can reduce a power consumption by reducing a current for charging a data bus between a memory core part and an output circuit. A single line data bus transmits read data output from the memory core part. A data bus drive circuit outputs the read read data to send to the single data bus. Each of a plurality of data latch circuits has a data input terminal connected to the data bus. A data input control circuit inputs the read data which is serially transmitted on the data bus to the data latch circuits in parallel in response to an operation of the data bus drive circuit. A data output control circuit outputs the latched read data in an order of latching by sequentially selecting outputs of the data latch circuits.

Semiconductor memory device having a single line data bus and latch

A semiconductor or memory device has a decoder circuit for decoding a plurality of external address signals. The external address signals include first and second external address signals. A first address buffer receives the first external address signals and outputs first internal address signals to first address lines. A second address buffer receives the second external address signals and outputs second internal address signals to second address lines. First predecoders have input terminals connected to the first address lines, and output first predecode signals to first predecode lines. Second predecoders have input terminals connected to the second address lines and output second predecode signals to second predecode lines. Main decoders have input terminals connected to the first predecode lines and the second predecode lines and output decode signals. The number of the first external address signals are greater than the number of the second external address signals. The second predecoders and the second predecode lines are provided at least in double in such a manner that inputs of the main decoders to be connected to each of the second predecode lines are equal in number to inputs of the main decoders to be connected to each of the first predecode lines. It is possible to shorten the transition time of predecode signals because of the same capacitive load of the predecoder circuit.

Decoder circuit for a semiconductor memory device

A semiconductor integrated circuit system includes a first power line which supplies a first source power voltage, and a second power line which supplies a second source power voltage. A first edge detecting unit outputs a first edge detection signal when a rising edge of the first source power voltage is detected. A second edge detecting unit outputs a second edge detection signal when a rising edge of the second source power voltage is detected. An output unit is connected to the first power line, and outputs data to a data terminal in a data output cycle and sets the data terminal in a high-impedance state in response to the first edge detection signal. An output control unit is connected to the second power line, and controls the output unit in accordance with a read-data signal in the data output cycle, and controls the output unit in response to the second edge detection signal, so that the data terminal is set in the high-impedance state by the output unit.

Semiconductor integrated circuit system

A semiconductor memory device includes gates which open in a data-write operation and a data-read operation to allow a passage of data therethrough, and a control circuit changing an open period of the gates between the data-write operation and the data-read operation.

Semiconductor memory device facilitating use of a high frequency clock

There are provided a sense amplifier driving circuit 900 applying a potential VCC/2 to wirings PSA and NSA when a block selecting signal BS0 is at a 'L', and applying a potential VCC to the wiring PSA via a pMOS transistor 91 and applying a grounding potential to the wiring NSA via an nMOS transistor 94 when the block selecting signal BS0 is at a 'H', and a LDB reset circuit 901A connected between the wiring PSA and a local data bus line pair LDB0 and *LDB0 and including pMOS transistors 95A and 96A which are closed/opened in correspondence to the open/closed state of a column gate 700.

Growing community of inventors

Kawasaki, Japan

Shusaku Yamaguchi