Hitachi, Ltd.

Hitachi Haramachi Semi-conductor, Ltd.

Hitachi Haramachi Electronics Co., Ltd.

Shuroku Sakurada

Tadashi Sakaue

Takahiro Nagano

Hidekatsu Onose

Shuji Musha

Yasuhiko Ikeda

Takehiro Ohta

Toshihide Ujihara

Hitoshi Komuro

Yoshiteru Shimizu

Hideo Kobayashi

Tadaaki Kariya

Hideyuki Yagi

Yoichi Nakashima

Yuji Takayanagi

Hitoshi Matsuzaki

Isamu Sanpei

Masayoshi Sugiyama

Isao Kojima

Takashi Saitoh

Sigeyasu Kouzuchi

Masaru Nakagawa

Shigeyasu Kouzuchi

Masafumi Ono

An auxiliary cathode lead is contacted to a cathode buffer electrode which contacts to an unit GTO arranged at the most remote region from a gate pressure contacting portion of a GTO pellet and the push-into effect of the auxiliary cathode current during the turn-off can be remarkably performed. Without inviting bad affects such as the increase in 'on' voltage, it is proposed a package structure of a semiconductor which the unit GTO arranged remote from a gate is easily to perform the turn-off. The maximum turn-off current can be heightened, it can easily correspond to the increase in the diameter of the pellet according to the large current of the unit element. Further, a condenser of a snubber circuit as a protection circuit of the unit GTO in a power inverter can be small, and the snubber loss can be lessened.

Semiconductor device and package structure therefore and power inverter

An insulated gate type semiconductor device has a gate electrode which controls current flow between two regions of the same conductivity type in a semiconductor substrate. A main electrode has a first portion contacting a first one of the two regions, a second portion extending above the gate electrode and a third portion providing a raised external contact surface to contact an external electrode. The gate electrode is insulated above and below by insulating films. To prevent damage to the gate electrode and the lower insulating films due to the pressure of the external electrode, there is a supporting insulating layer on the surface of the substrate underlying the contact portion of the main electrode and having a thickness substantially greater than the thickness of the insulating film below the gate electrode and the contact surface is more remote from the substrate than the second portion of said main electrode.

Insulated gate type semiconductor device in which the reliability and

A gate turn-off thyristor including: an n-type emitter semiconductor layer divided into a plurality of n-type areas; a p-type base semiconductor layer which cooperates with the n-type emitter semiconductor layer to form a first main circular surface; an n-type base semiconductor layer; and a p-type emitter semiconductor layer cooperating with the n-type base semiconductor layer to form a second main circular surface. An outer diameter of the p-type emitter semiconductor layer is smaller than that of the n-type emitter semiconductor layer. A first main electrode put in low resistance contact with the n-type emitter semiconductor layer is formed on the first main surface. A second main electrode put in low resistance contact with the p-type emitter layer and the n-type base semiconductor layer is formed on the second main surface. A control electrode is formed in the p-type base semiconductor on the first main surface. A first electrode plate larger in diameter than the n-type emitter semiconductor layer is connected electrically with the first main electrode. A second electrode plate larger in diameter than the n-type emitter semiconductor layer is connected electrically with the second main electrode.

Gate turn-off thyristor

A gate turn-off (GTO) thyristor has a plurality of unit GTO thyristors of strip-like configuration in a same semiconductor substrate, each unit GTO thyristor being constructed of an N emitter layer, P base layer, N base layer and P emitter layer. The P base and N base layers are shared in common for all the unit GTO thyristors which are formed in a multi-ring configuration. The exposed area of the P emitter layer of a unit GTO thyristor located far from the gate signal input area is made smaller than that of the P emitter layer of a unit GTO thyristor located relatively close to the gate signal input area.

Gate turn-off thyristor of multi-emitter type

A gate turn-off (GTO) thyristor has a plurality of unit GTO thyristors of strip-like configuration in a same semiconductor substrate, each unit GTO thyristor being constructed of an N emitter layer, P base layer, N base layer and P emitter layer. The P base and N base layers are shared in common for all the unit GTO thyristors which are formed in a multi-ring configuration. The exposed area of the P emitter layer of a unit GTO thyristor located far from the gate signal input area is made smaller than that of the P emitter layer of a unit GTO thyristor located relatively closer to the gate signal input area.

A semiconductor substrate of the shape of a disc possesses a first main surface and a second main surface. The semiconductor substrate consists of an emitter layer on the side of the cathode, a second base layer, a first base layer, and an emitter layer on the side of the anode, which are laminated in the order mentioned from the side of the cathode toward the side of the anode. The circumference of the emitter layer on the anode side is short-circuited by an emitter short-circuiting layer on the anode side. On the second main surface is arrayed the emitter layer on the cathode side being divided into a plurality of strip units which are oriented in a radial manner from the center toward the periphery of the semiconductor substrate. The second base layer is exposed on the other portions on the second main surface. The emitter layers on the anode side are provided in the portions where the emitter layers on the cathode side are projected onto the anode side. The emitter short-circuiting layer on the anode side forms a plurality of fan-shaped portions which are oriented in a radial manner from the center toward the periphery of the semiconductor substrate so that the area per unit length in the radial direction of the emitter short-circuiting layer increases from the center toward the periphery. The emitter layers on the anode side and the emitter short-circuiting layers on the anode side are exposed to the first main surface, and are brought into contact with the anode electrodes. The emitter layers on the cathode side are in contact with the cathode electrodes, respectively. The second base layer is in contact with the control electrode, and a lead wire is connected to a central portion of the circular control electrode.

A pressure contact semiconductor device has a semiconductor substrate disposed on a metal post electrode through metal electrode plate, an insulating ring engaged with the periphery of the metal post electrode extends to the periphery of the metal electrode plate and is brought into contact therewith at a certain height with a sufficient contact pressure. The semiconductor substrate is positioned precisely with respect to the metal post electrode so that a gate electrode ring is precisely positioned on a gate electrode film formed on the upper surface of the semiconductor substrate.

Pressure contact semiconductor device

A gate turn-off thyristor is provided having a semiconductor substrate, an anode electrode, a cathode electrode and a gate electrode. The semiconductor substrate includes a P emitter layer connected to the anode electrode, an N base layer adjacent to the P emitter layer, a P base layer adjacent to the N base layer and connected to a gate electrode, and an N emitter layer adjacent to the P base layer and connected to the cathode electrode. In order to improve in its current cut-off performance, the semiconductor substrate further includes a P-type layer provided between the P emitter layer and the N base layer and having the impurity concentration lower than that of the N base layer.

Gate turn-off thyristor with integral capacitive anode

A semiconductor device having a semiconductor region of a high impurity concentration which is exposed to one major surface of a semiconductor pellet and has a plurality of split areas, and one main electrode on the major surface which makes low ohmic contact with the semiconductor region and has a bonding pad area for lead connection, comprises the high impurity concentration region underlying the entirety of the main electrode inclusive of the bonding pad, and an insulating film interposed between the bonding pad and the semiconductor region. In a gate turn-off thyristor with a short-circuiting P base region, the semiconductor region constitutes an N emitter region and an area thereof underlying the insulating film prevents the cathode/gate short and current concentration by lateral resistance upon turning off the device by the gate bias. In a bipolar transistor, the semiconductor region constitutes an emitter.

Power semiconductor device

A gate turn-off thyristor of a short-circuited emitter configuration comprises a semiconductor substrate of a P.sub.E -N.sub.B -P.sub.B -N.sub.E four-layer structure, wherein a P.sub.E -layer is short-circuited through a N.sub.B -layer and an anode. The N.sub.B -layer includes heavily doped regions to which the anode is ohmic contacted with a low resistance. The P.sub.E -layer is provided at a location at least covered by a projection of the N.sub.E -layer. The thickness of the heavily doped regions is greater than that of the P.sub.E -layer. The improved structure assures satisfactory gate turn-off characteristics, although the semiconductor substrate is not doped with a life time killer impurity.

Gate turn-off thyristor with selective anode penetrating shorts

This invention concerns a so-called double-moat uni-surface type semiconductor device in which two concentric moats are provided in one main surface of the substrate and the edges of the two pn-junctions for blocking main circuit voltages applied to the device are exposed in the surfaces of the moats. Semiconductor layers having high impurity concentrations and serving as channel stoppers are formed on the semiconductor layers exposed in the one main surface of the substrate, contiguous to the moats and spaced apart from the pn-junctions, each high impurity concentration layer having the same conductivity type as the semiconductor layer on which it is formed. The moats are filled with surface passivating material.

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Katsuta, Japan

Shuroku Sakurada