Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Shuou Nomura

Akira Moriya

Hajime Matsui

Takaya Ogawa

Hirotsugu Kajihara

Tomoya Suzuki

Kazuhiro Hiwada

Shunichi Ishiwata

Atsushi Mochizuki

Shintaro Sano

Kazuyo Kanou

Yoshiro Tsuboi

Yoshihisa Iwata

Toshikatsu Hida

Kosuke Hatsuda

Kosuke Tatsumura

Shinichi Yasuda

Kohei Oikawa

Masato Oda

Koichiro Zaitsu

Mari Matsumoto

Ryo Yamaki

Youhei Fukazawa

Kojiro Suzuki

Yukimasa Miyamoto

Kazuki Inoue

Yuki Ando

Yuki Mandai

A memory system includes a nonvolatile memory including memory cells, and a memory controller. The memory controller is configured to read first data through application of a first read voltage to each of the memory cells, perform a first decoding process with respect to the first data, when the first decoding process fails, perform a tracking process. The tracking process includes reading second data indicating a threshold voltage level of each of the memory cells through application of a plurality of second read voltages to each of the memory cells, and obtaining, with respect to each of the memory cells, likelihood information using the second data. The second read voltages are shifted by a predetermined amount. The memory controller is further configured to perform a second decoding process with respect to the second data using the likelihood information.

Memory system and memory control method

A storage system is provided, including: a host including a memory, the memory including a submission queue and a completion queue and being configured to store update frequency information; and a memory system configured to be connectable with the host and including a nonvolatile memory and a controller, the controller configured to control the nonvolatile memory, to receive the update frequency information of the submission queue from the host, to read command information stored in the submission queue based on the received update frequency information, and to execute controlling for the nonvolatile memory based on the command information.

Memory system and control method controlling nonvolatile memory in accordance with command issued by processor

According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to be connectable with a host and control the nonvolatile memory. The controller is configured to receive update frequency information of a submission queue from the host, read command information stored in the submission queue in accordance with the update frequency information, and execute controlling for the nonvolatile memory based on the command information.

According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a memory string including memory cells including first to third memory cells, and a selection transistor connected to the memory cells, and first to third word lines that are connected to gates of the first to third memory cells of the memory string. The memory controller reads data of the first to third memory cells by applying first to third read voltages to the first to third word lines, respectively. The memory controller reads second data by applying a fourth read voltage to the second word line in parallel to processing of decoding first data, obtains likelihood information on the basis of the first data, the second data, and at least one of the third data and the fourth data, and decodes data on the basis of the likelihood information.

Memory system and method of controlling nonvolatile memory

According to one embodiment, a memory system includes a nonvolatile first memory, a volatile second memory, a capacitor, and a memory controller. The nonvolatile first memory includes a storage region that includes a plurality of memory cells. The capacitor is configured to accumulate electric power. The memory controller writes first data stored in the volatile second memory to the storage region in a first mode, using a power supply from outside. The first mode is a mode in which one-bit data is written to each of the memory cells. The memory controller writes, upon stop of the power supply from the outside, the first data to the storage region in a second mode, using the electric power accumulated in the capacitor. The second mode is a mode in which one-bit data is written to each of the memory cells and is different from the first mode.

Memory system including a nonvolatile memory and a volatile memory, and method

According to one embodiment, a video transmission system includes a coding apparatus for compressing a plurality of input images and a decoding apparatus for extending the compressed images. The coding apparatus includes a predictive coding unit that generates predictive error data based on a reference image and an input image, a data compression unit that compresses the predictive error data, an image storage unit that stores the compressed input image in a frame memory in the compressed state or compresses a local decoded image and stores the compressed local decoded image in the frame memory, and an image extension unit that extends an image stored in the frame memory. The decoding apparatus includes a data extension unit that extends the predictive error data, and a predictive decoding unit that acquires the completely decoded input image as the reference image and newly decoding the input image based on the acquired reference image and the predictive error data.

Video transmission system, coding apparatus, and moving picture compression method

A decoding device according to an embodiment includes: a reception memory for storing received image; a frame buffer for storing a reference image; a decoding unit for decoding the received image based on the reference image stored in the frame buffer; a reference image storage for storing the decoded image, decoded by the decoding unit, in the frame buffer as the reference image; and an output image selection unit for selecting the reference image stored in the frame buffer as an output image when the reception memory underflows and selecting the decoded image as the output image when the reception memory does not underflow.

Decoding device, image transmission system, and decoding method

According to one embodiment, a semiconductor apparatus includes a block and a controller. The block includes a logic circuit and a routing module. The routing module includes a plurality of first wiring lines, a plurality of second wiring lines, switches, and a wiring line switching circuit. The switches are arranged to perform connection and disconnection between the first wiring lines and the second wiring lines. The wiring line switching circuit is arranged to switch a wiring line for transmitting the signal, among the first wiring lines and the second wiring lines. The controller is arranged to control driving of the switches and the wiring line switching circuit.

Semiconductor apparatus, routing module, and control method of semiconductor apparatus

According to one embodiment, an image output device includes a buffer into which video information input in stream data is written per block, a determination unit configured to determine whether the buffer is in an overflow state due to slow reproduction, and a buffering control unit configured to switch a buffering pattern of the video information based on a determination result of the determination unit.

Image output device, image output method, and recording medium

A moving image player device of the present invention includes an interpolated image generating unit that generates an interpolated frame corresponding to a time between two adjacent input frames using two input frames among the plurality of input frames, and a video playing unit that detects a scene change in the video, outputs the plurality of input frames or the interpolated frames in time series based on the detection result, and plays the video at an arbitrary playing speed. When the scene change is detected, the video playing unit skips a display of the interpolated frames corresponding to time between an input frame at the end of a first scene and an input frame at the head of a second scene, and displays an input frame of the second scene or the interpolated frame after the input frame at the end of the first scene or the interpolated frame.

Moving image player device

According to one embodiment, a programmable logic switch includes first and second word lines above a first path transistor, a first pillar passing through the first and second word lines and connected to the first path transistor, a second pillar passing through the first and second word lines and connected to the first path transistor, a first memory device between the first pillar and the first word line, a second memory device between the first pillar and the second word line, a third memory device between the second pillar and the first word line, and a fourth memory device between the second pillar and the second word line.

Programmable logic switch

A processing device disclosed herein comprises: a memory access circuit which accesses a memory and sequentially reads data from the memory based on a predetermined access pattern; storage in which the data read by the memory access circuit is stored, wherein the memory access circuit sequentially reads the data from the memory and stores the data in storage until storage is full; and a processor which acquires the data from storage.

Processing device

An arithmetic code decoding apparatus including a context index predictor which predicts a context index, a pipeline arithmetic code decoder which executes a decoding process of the bitstream using the predicted context index and outputs a decoded symbol based on prediction, a context index generator which receives the previous decoded symbols, the syntax element, and context information of the bitstream, and generates a correct context index, a binarization table searcher which searches the binarization table using the decoded symbol for a value of the syntax element, and a prediction failure detector which outputs a prediction failure signal when the two context indices do not match, wherein when the prediction failure signal is output, the pipeline arithmetic code decoder flashes the decoding process executed using the predicted context index, re-executes a decoding process using the correct context index, and outputs a correct decoded symbol.

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Yokohama, Japan

Shuou Nomura