Mstar Semiconductor, Inc.

Mediatek Corporation

Avid Electronics Corp.

Shuo-Yuan Hsiao

Chao-Tung Yang

Yao-Chi Wang

Fu-Cheng Wang

Fucheng Wang

Sheng-Che Tseng

Jian-Yu Ding

Yuan-Yu Fu

Shoufang Chen

Ming-Chung Liu

Shen-Ching Sun

Manxia Xiao

Chieh-En Yu

Chao-Chun Sung

A buffer circuit and a multiplexer using the buffer are provided. The buffer may selectively operate at a first mode or a second mode. The buffer includes a first signal input terminal, a first signal output terminal, and a path circuit coupled between the first signal input terminal and the first signal output terminal. The path circuit has a voltage source terminal. In response to the buffer operating at the first mode, a first signal transmission path is formed in the path circuit and between the first signal input terminal and the first signal output terminal. The first signal transmission path is disconnected from the voltage source terminal.

Buffers and multiplexers

The present invention provides an oscillator including a tapped inductor and a cross-coupled pair. The tapped inductor includes a first terminal, a second terminal, a first tap and a second tap. The cross-coupled pair receives two input signals from the first terminal and the second terminal to generate two output signals to the first tap and the second tap, respectively.

Oscillator with tapped inductor

A direct-conversion transmitter including an oscillator, a frequency divider, a transmitter, and a filter is provided. The oscillator generates an oscillating signal with an original frequency. The frequency divider performs frequency dividing on the oscillating signal, so as to generate a carrier signal. The transmitter receives the carrier signal from the frequency divider and generates an output signal based on the carrier signal and a data signal. The filter is coupled between the frequency divider and the transmitter. The filter filters out an interference signal fed-back from the transmitter to the oscillator, wherein the interference signal may cause the oscillating signal to float.

Direct conversion transmitter and communication system utilizing the same

A signal processing apparatus for a multi-mode satellite positioning system includes a band-pass filter, a local oscillator circuit, a first mixing circuit, a second mixing circuit, an analog-to-digital converter and a baseband circuit. By properly allocating a local frequency, radio frequency (RF) signals of a Global Positioning System (GPS), a Galileo positioning system and a Global Navigation System (GLONASS) are processed via a single signal path to save hardware cost.

Signal processing apparatus for multi-mode satellite positioning system and method thereof

A proportional to absolute temperature (PTAT) sensor is capable of reducing a sensing error resulted from a mismatch between circuit components. The PTAT sensor includes a control unit, a sensing unit and a calculation unit. The control unit generates a control signal. The sensing unit, comprising at least a pair of circuit components having a matching relationship, senses an absolute temperature under the first connection configuration and the second connection configuration respectively to generate a first voltage value and a second voltage value, wherein the first connection configuration and the second connection configuration are decided by interchanging the circuit connections of the pair of circuit components according to the control signal. And the calculation unit, coupled to the sensing unit, calculates a PTAT voltage value according to the first voltage value and the second voltage values.

PTAT sensor and temperature sensing method thereof

A multi-modulus divider and a method for performing frequency dividing by utilizing a multi-modulus divider are disclosed. The multi-modulus divider comprises a multi-modulus dividing circuit, a pulse generating circuit, and a modulus signal generating circuit. The multi-modulus dividing circuit comprises several serially connected divider cells, of which a predetermined one may be bypassed. The multi-modulus dividing circuit generates an output frequency according to an input frequency and a divisor. A range of the divisor comprises a plurality of numerical intervals. The pulse generating circuit generates a pulse signal. The modulus signal generating circuit generates a determination result by determining which numerical interval the divisor belongs to, and inputs, according to the determination result, the pulse signal into the predetermined divider cell to be one of references which the predetermined divider cell refers to when outputting a modulus signal. The predetermined divider cell corresponds to the determination result.

Multi-modulus divider with extended and continuous division range

A mixer in a smaller signal differential model includes a load circuit, a switch quad, and a transconductor. The switch quad further including a first current path and a second current path is coupled to the load circuit. The connecting node of the switch quad and the load circuit is a differential-output terminal. The transconductor further includes a first resistor, a first operational amplifier, a second operational amplifier, a first current mirror, and a second current mirror. The resistor is coupled between two first input terminals of the first operational amplifier and the second operational amplifier. A current control terminal of the first current mirror is coupled to the first input terminal of the first operational amplifier, and a current mirroring terminal of the first current mirror is coupled to the first current path. A current control terminal of the second current mirror is coupled to the first input terminal of the second operational amplifier, and a current mirroring terminal of the second current mirror is coupled to the second current path. A differential voltage is applied between two second input terminals of the first operational amplifier and the second operational amplifier.

Mixer circuit

A quadrature oscillator capable of lowering phase noise and power dissipation is disclosed. The oscillator circuit includes two symmetrical oscillators ( ) ( ) formed by cross-coupled transistor pairs with positive feedback structure to produce negative resistance, two LC circuits ( ) ( ) coupled to the above oscillators ( ) ( ) to produce positive resistance offsetting the negative resistance through the oscillators ( ) ( ), and two coupling circuits ( ) ( ) coupled to the oscillators ( ) ( ) to produce quadrature phase outputs, wherein, the transistor pairs in each coupling circuit ( ) are respectively connected to the corresponding transistor pairs in the two oscillators ( ) ( ), to prevent the operating point of the oscillator transistors from shifting toward the linear region.

Growing community of inventors

Hsinchu, Taiwan

Shuo-Yuan Hsiao