Taiwan Semiconductor Manufacturing Comp. Ltd.

Shuo-Yen Chou

Ru-Gun Liu

Shih-Ming Chang

Hsu-Ting Huang

Ken-Hsien Hsieh

Minfeng Chen

Chin-Hsiang Lin

Shinn-Sheng Yu

Chih-Jie Lee

Kenji Yamazoe

Dong-Yo Jheng

Chih-Chiang Tu

Wen-Hao Cheng

Pi-Tsung Chen

Jue-Chin Yu

Zengqin Zhao

Lun Hsieh

Tsai-Sheng Gau

Chi-Ming Tsai

Chien-Wen Lai

Chien Wen Lai

Hoi-Tou Ng

Yi-Yin Chen

A method includes receiving a layout for fabricating a mask, determining a plurality of target contours corresponding to a plurality of sets of lithographic process conditions, determining a modification to the layout, simulating the modification to the layout under the plurality of sets of lithographic process conditions to produce a plurality of simulated contours, determining a cost of the modification to the layout based on comparisons between the plurality of simulated contours and corresponding ones in the plurality of target contours, and providing the modification to the layout for fabricating the mask based at least in part on the cost being within a predetermined threshold.

Optical proximity correction and photomasks

A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)−2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.

Method of manufacturing a semiconductor device and apparatus for manufacturing the semiconductor device

A method includes receiving a layout for fabricating a mask, determining a first target contour corresponding to a first set of process conditions, determining a second target contour corresponding to a second set of process conditions, simulating a first potential modification to the layout under the first set of process conditions to generate a first simulated contour, simulating a second potential modification to the layout under the second set of process conditions to generate a second simulated contour, evaluating costs of the first and second potential modifications based on comparing the first and second simulated contours to the first and second target contours, respectively, and providing the layout and one of the first and second potential modifications having a lower cost for fabricating the mask. The first set of process conditions is different from the second set of process conditions.

A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)&#x2212;2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.

Photolithography apparatus includes a radiation source, a mask to modify radiation from the radiation source so the radiation exposes photoresist layer disposed on a semiconductor substrate in patternwise manner, a wafer stage, and a controller. The wafer stage supports the semiconductor substrate. The controller determines target total exposure dose for the photoresist layer and target focus position for the photoresist layer; and controls exposure of first portion of the photoresist layer to first exposure dose of radiation at first focus position using first portion of the mask, moving the semiconductor substrate relative to the mask; and exposure of the first portion of the photoresist layer to second exposure dose of radiation using second portion of the mask at second focus position, and exposure of second portion of the photoresist layer to the second exposure dose at the second focus position using the first portion of the mask.

A method includes receiving a layout that includes a shape to be formed on a photomask and determining a plurality of target lithographic contours for the shape, wherein the plurality of target lithographic contours includes a first target lithographic contour for a first set of process conditions and a second target lithographic contour for a second set of process conditions, performing a lithographic simulation of the layout to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions, determining a first edge placement error between the first simulated contour and the first target lithographic contour and a second edge placement error between the second simulated contour and the second target lithographic contour, and determining a modification to the layout based on the first edge placement error and the second edge placement error.

A method includes providing a photomask having a patterned absorption layer over a substrate. The photomask is irradiated with a beam having a mixture of transverse electronic (TE) waves and transverse magnetic (TM) waves. The irradiating includes generating surface plasmonic polaritons (SPP) on a sidewall of the patterned absorption layer. The SPP is used to suppress the TM waves while reflecting the TE waves. A target substrate is exposed to TE waves.

Photomask design for generating plasmonic effect

A method includes establishing a simulation process for simulating fabrication of a structure on a wafer. The simulation process includes multiple simulation steps for simulating multiple wafer fabrication steps respectively, and further includes a step of testing the structure that produces a result representing quality of the structure. Each of the simulation steps has a respective adjustable process parameter. The method further includes specifying a respective workable range for each process parameter and running the simulation process in iterations using a wafer process simulator until the result becomes optimal. During the running of the simulation process, every two consecutive iterations either adjust two different process parameters within their workable ranges or adjust a same process parameter at opposite directions within its workable range.

Method for optimized wafer process simulation

Various examples of a technique for performing optical proximity correction and for forming a photomask are provided herein. In some examples, a layout is received that includes a shape to be formed on a photomask. A plurality of target lithographic contours are determined for the shape that includes a first target contour for a first set of process conditions and a second target contour that is different from the first target contour for a second set of process conditions. A lithographic simulation of the layout is performed to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions. A modification to the layout is determined based on edge placement errors between the first simulated contour and the first target contour and between the second simulated contour and the second target contour.

A pattern modification method and a patterning process are provided. The method includes extracting a first pattern and a second pattern to be respectively transferred to a first target portion and a second target portion of a resist layer. The method also includes obtaining regional information of the first target portion and the second target portion. The method includes determining a first desired focus position for transferring the first pattern based on the regional information. In addition, the method includes determining a second desired focus position for transferring the second pattern based on the regional information. The method includes modifying one or both of the first pattern and the second pattern. As a result, focus positions of the first pattern and the second pattern are shifted to be substantially and respectively positioned at the first desired focus position and the second desired focus position during an exposure operation.

Pattern modification and patterning process

Source beam optimization (SBO) methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an integrated circuit (IC) design layout and performing an SBO process using the IC design layout to generate a mask shot map and an illumination source map. The SBO process uses an SBO model that collectively simulates a mask making process using the mask shot map and a wafer making process using the illumination source map. A mask can be fabricated using the mask shot map, and a wafer can be fabricated using the illumination source map (and, in some implementations, using the mask fabricated using the mask shot map). The wafer includes a final wafer pattern that corresponds with a target wafer pattern defined by the IC design layout. The SBO methods disclosed herein can significantly reduce (or eliminate) variances between the final wafer pattern and the target wafer pattern.

Source beam optimization method for improving lithography printability

Target optimization methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an IC design layout for a target pattern, wherein the target pattern has a corresponding target contour; modifying the target pattern, wherein the modified target pattern has a corresponding modified target contour; and generating an optimized target pattern when the modified target contour achieves functionality of the target pattern as defined by a constraint layer. The method can further include defining a cost function based on the constraint layer, where the cost function correlates a spatial relationship between a contour of the target pattern and the constraint layer.

Target optimization method for improving lithography printability

A system and method that includes receiving a layout of an integrated circuit (IC) device. A template library is provided having a plurality of parameterized shape elements. A curvilinear feature of layout is classified by selecting at least one of the parameterized shape elements that defines the curvilinear feature. A template index is associated with the layout is formed that includes the selected parameterized shape element. The template index and the layout can be delivered to a mask writer, which uses the template index and the layout to fabricate a pattern on a photomask.

Growing community of inventors

Hualien County, Taiwan

Shuo-Yen Chou