University of Florida Research Foundation Inc

Future Wei Technologies, Inc.

Google Inc.

The University of Texas System

Huawei Technologies Co., Limited

Shuo Wang

Hui Zhao

Amirhossein Moeini

Le Yang

Huan Zhang

Heping Dai

Yiming Li

Boyi Zhang

Swarup Bhunia

Robert Parker

Srikanth Lakshmikanthan

Honggang Sheng

Prabuddha Chakraborty

Rohan Reddy Kalavakonda

Juntao Yao

Yanwen Lai

Yingjie Zhang

Yongbin Chu

Apparatus, systems, and methods described herein relate generally to on-the-go entity-to-entity charging for multi-level battery-powered entities in transportation systems. A method can include determining charge levels, current positions, battery configuration, and transport speeds for an electric vehicle (EV), identifying one or more EVs in need of charging, and mobilizing a nearby EV for on-the-go peer-to-peer charging. A processor, with a memory including computer program code, can be configured to receive current charge level data for mobile battery-powered entities, identify one or more EVs to be charged and one or more other EVs that have excess charge to transfer, and send charging instructions to the EVs. A routing and charge transaction scheduling algorithm can be used to optimize the route of one or more battery-powered entities and to schedule charge transactions between EVs and/or a charging entity. A heuristic battery architecture compiler can be used to optimize battery architecture.

Multi-level battery systems for battery-operated entities, methods for rapid charge transfer therebetween, and methods for optimizing entity routing and network charge distribution

A multi-phase coupled inductor can include: an upper E core including a first upper limb, a second upper limb, and a third upper limb; a lower E core including a first lower limb, a second lower limb, and a third lower limb; a first winding to wind the first upper limb and the first lower limb; a second winding to wind the second upper limb and the second lower limb; a third winding to wind the third upper limb and the third lower limb; a fourth winding to wind the first lower limb; and a fifth winding to wind the third lower limb. A first phase current can flow from the first winding to the fifth winding, and a third phase current can flow from the third winding to the fourth winding.

Multi-phase coupled inductor having compensation windings

Provided are examples of electromagnetic interference (EMI) filters for reducing radiated EMI in power converters. An example EMI filter includes a common mode (CM) choke located on an input cable connected to a first side of a converter a first set of Y-capacitors located between a primary ground (PGND) node of the converter and a secondary ground (SGND) node of the converter, and a second set of Y-capacitors located between the first side of the converter and the SGND node. A first shielding may be connected to the SGND node. One or more additional shieldings may be inside the first shielding and connected to one of the PGND node or the SGND node. The converter may be one or more of an isolated converter, an LLC resonant power converter, a Flyback converter, a forward converter, or a push-pull power converter.

Common mode (CM) electromagnetic interference (EMI) filters for reducing radiated EMI in power converters

An integrated common mode and differential mode inductor can include a first core including a first center leg, a second core including a second center leg, a first center winding on the first center leg, and a second center winding on the second center leg. The first center leg can be spaced apart from the second center leg, for example by a center air gap. The integrated common mode and differential mode inductor can further include a left winding on a first left leg of the first core and a second left leg of the second core, as well as a right winding on a first right leg of the first core and a second right leg of the second core.

Integrated common mode and differential mode inductors with low near magnetic field emission

Systems and methods are configured to control DC side current harmonics of a cascaded H-bridge (CHB) converter that includes a plurality of cells. In various embodiments, an odd-order current harmonic is injected at the AC side of the CHB converter based on an optimization of a constrained optimization problem to achieve at least one of balancing the DC side current harmonics of the plurality of cells, reducing the DC side current harmonics of the plurality of cells, and meeting the requirements of the IEEE 519 standard. The optimization problem may include a cost function based on switching transitions of the CHB converter and at least one constraint based on, for example, an AC side current harmonic, a maximum demand load current of the CHB converter base on the IEEE 519 standard, and a zero-order current harmonic and an hth-order current harmonic for each cell of the CHB converter.

Cascaded H-bridge converters for battery energy storage systems

Inductor designs and methods are provided. An inductor can include a first core and a second core. The first core can be larger than the second core and the second core can be seated within the inner diameter of the first core. A first and a second wire can be provided that each wrap around the first core and the second core. The first core can have less windings than the second core.

Inductor designs for reducing magnetic interference

Techniques to diagnose internal short circuits (ISCs) of a lithium-ion battery (LIB) are disclosed. The short circuit resistance data can help to detect the ISCs of a LIB as fast as possible. For the proposed detection techniques, a resistor-based circuit and an inductor-based circuit are disclosed for single-cell LIBs as well as for LIBs having multiple cells. Two topologies of the resistor-based circuits are disclosed to detect the ISCs of multi-cell LIBs.

Fast and precise detection of an internal short circuit on a lithium-ion battery

Methods and apparatus for reducing Miller effect in SiC MOSFETs are provided. An example apparatus includes a plurality of SiC MOSFETs and a Miller current cancellation circuit configured to mitigate Miller current induced by switching transients associated with the plurality of SiC MOSFETS. The Miller current cancellation circuit includes a two-stage voltage sampling circuit configured to sample a drain to source voltage of a SiC MOSFET of the plurality of SiC MOSFETs, a voltage inverting circuit configured to invert the sampled drain to source voltage, and an injection capacitor configured to generate, by way of receiving the inverted sampled drain to source voltage as input, inverse Miller current to mitigate the Miller current within the plurality of SiC MOSFETS.

Method and apparatus for eliminating crosstalk effects in high switching-speed power modules

Various examples related to electromagnetic interference (EMI) energy mitigation techniques are provided. In one example, a method includes determining electromagnetic interference (EMI) spectrum information based upon switching angles of a switching circuit and processing harmonic magnitudes (C) associated with the switching angles using an artificial neural network to determine adjusted switching angles for the switching circuit; and applying the adjusted switching angles to control the switching circuit thereby reducing generated EMI energy by the switching circuit.

EMI energy mitigation

A device comprises a magnetic core comprising a first leg and a second leg formed by a first magnetic component and a second magnetic component, wherein a first gap and a second gap are placed between the first magnetic component and the second magnetic component and are in the first leg and the second leg, respectively, a first winding wound around the first leg in a counter-clockwise direction and a second winding wound around the second leg in a clockwise direction.

Inductor structure and method for forming the same

A hybrid Cascaded H-Bridge (CHB) converter includes a selective harmonic current mitigation pulse width modulation (SHCM-PWM) unit coupled to an input current and providing an output signal SW, a phase shift pulse width modulation (PSPWM) unit coupled to the input current and providing an output signal SW, a modulation selector coupled to the output signal SWof the SHCM-PWM unit and the output signal SWof the PSPWM unit and providing an output signal SW, and a CHB converter coupled to the output signal SW of the modulation selector. The modulation selector can select one of the output signals (SWand SW) as the output signal SW based on the input current. The hybrid technique is for cascaded multilevel converters which utilizes asymmetric SHCM to mitigate the harmonics generated from PS-PWM to meet harmonic limits with a smaller number of switching transitions and smaller inductance than the conventional PS-PWM technique.

Control to output dynamic response and extend modulation index range with hybrid selective harmonic current mitigation-PWM and phase-shift PWM for four-quadrant cascaded H-bridge converters

A full bridge LLC resonant converter can include: a full bridge circuit including a first input node and a second input node; a LLC resonant tank circuit connected to the first input node and the second input node; a transformer winding part connected to the LLC resonant tank circuit; a rectifier circuit connected to the transformer through a first output node and a second output node; and a capacitor connected between the first input node and the first output node. The LLC resonant tank circuit can include a resonant capacitor connected to the first input node, a resonant inductor connected to the resonant capacitor, and a magnetizing inductance connected between the resonant inductor and the second input node.

Loop noise balance technique for CM EMI noise reduction of the full bridge LLC resonant converter

Four quadrant modulation techniques that can synthesize a full range solution or a full modulation index range are provided. Such techniques can be applied to a DC/AC inverter, an AC to DC rectifier, and AC/DC/AC topology. The techniques can also be applied to a neutral point clamped (NPC) topology, flying capacitor (FLC) topology, cascaded H-bridge (CHB) topology, modular multilevel topology, modular multilevel converters, and multimodule converters.

Four-quadrant modulation technique to extend modulation index range for multilevel selective harmonic elimination / compensation

A hybrid Cascaded H-Bridge (CHB) converter can include a selective harmonic current mitigation pulse width modulation (SHCM-PWM) unit coupled to an input current and providing an output signal SW, a phase shift pulse width modulation (PSPWM) unit coupled to the input current and providing an output signal SW, a modulation selector coupled to the output signal SWof the SHCM-PWM unit and the output signal SWof the PSPWM unit and providing an output signal SW, and a CHB converter coupled to the output signal SW of the modulation selector. The modulation selector can select one of the output signals (SWand SW) as the output signal SW based on the input current.

Various examples related to electromagnetic interference (EMI) energy mitigation techniques are provided. In one example, a method includes adjusting switching angles of a switching circuit based on resolution bandwidths (RBWs) associated with an EMI frequency spectrum of the switching circuit and weight coefficients of the RBWs. The total energy of the switching circuit can be reduced by adjusting an average duty cycle of the switching circuit. EMI spectrum information can be determined based upon switching angles of a switching circuit. For example, weighted errors corresponding to differences between reference harmonic magnitudes and determined harmonic magnitudes can be determined. In response to a comparison of a maximum weighted error to a preset tolerance threshold, adjustment to the switching angles can be determined and/or applied.

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Gainesville, FL, United States of America

Shuo Wang