Macronix International Co., Ltd.

Shuo-Lun Tu

Shih-Chin Lien

Shyi-Yuan Wu

Cheng-Chi Lin

Hsin-Liang Chen

Ming-Tung Lee

Hsueh-I Huang

Jiun-Yan Tsai

Wing-Chor Chan

Ching-Lin Chan

Chin-Pen Yeh

Chin-Wei Chang

Chin-Shien Lu

Wei-Hsun Hsu

A semiconductor device includes: a substrate; a source region and a drain region located in the substrate; a gate structure located in the substrate between the source region and the drain region; an insulating layer located between the gate structure and the drain region; a plurality of field plates located on the insulating layer, wherein the field plate closest to the gate structure is electrically connected to the source region; a first well region located in the substrate; a body contact region located in the first well region, wherein the body contact region is electrically connected to the source region and the field plate closest to the gate structure; and a first doped drift region located in the substrate, wherein the gate structure is located between the first well region and the first doped drift region, and the drain region is located in the first doped drift region.

Semiconductor device and method of fabricating the same

A lateral drain metal oxide semiconductor (LDMOS) device includes a well region having a second conductive type in a substrate, a body region having a first conductive type in the well region, a drift region having the second conductive type in the well region and spaced apart from the body region, a source region having the second conductive type in the body region, a drain region having the second conductive type in the drift region, a gate structure on the well region between the source region and the drain region, a shallow trench isolation (STI) structure in the drift region between the drain region and the source region, and a buried layer having the first conductive type in the well region under the drift region, a center of the buried layer being aligned with a center of the STI structure.

Semiconductor device and method of fabricating same

A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process.

Method of fabricating integrated semiconductor device and structure thereof

A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates and one or more P+ doped plates.

Bi-directional bipolar junction transistor for high voltage electrostatic discharge protection

A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.

Method of fabricating integrated semiconductor device with MOS, NPN BJT, LDMOS, pre-amplifier and MEMS unit

An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra N-type layer that reduces recombination of electrons and holes.

High-beta bipolar junction transistor and method of manufacture

A bi-directional triode thyristor (TRIAC) device for high voltage electrostatic discharge (ESD) protection may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates and one or more P+ doped plates. The portion of the N-type well region that is interposed between the two P-type well regions may comprise one or more P-type portions, such as a P+ doped plate or a P-type implant.

Bi-directional triode thyristor for high voltage electrostatic discharge protection

A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collector electrode are separated from each other by the well region. The conductive layer is on the well region between the base electrode and the collector electrode.

Structure of NPN-BJT for improving punch through between collector and emitter

A bipolar junction transistor (BJT) device including a base region, an emitter region and a collector region comprises a substrate, a deep well region in the substrate, a first well region in the deep well region to serve as the base region, a second well region in the deep well region to serve as the collector region, the second well region and the first well region forming a first junction therebetween, and a first doped region in the first well region to serve as the emitter region, the first doped region and the first well region forming a second junction therebetween, wherein the first doped region includes a first section extending in a first direction and a second section extending in a second direction different from the first direction, the first section and the second section being coupled with each other.

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Hsinchu, Taiwan

Shuo-Lun Tu